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INH @H߾1HBLXI 1H5z- HHH1L #I 1H5- H߾H1H 1H5h- H߾HH1H 1H5:- H HHI1H 1H5- H HHQI1dH 1H5;, H HHI1/H 1H5, H xHHI1G H޿ $< foc1HCommit_0f0H5HHt_0_cycHHCommit_1HHt_1_cycHHCommit_2HHt_2_cyc) H+ H߾H1DG 1H5޵+ H߾H1G 1H5G+ AULHAWLH¾L1F 1H5M+ _AXHH1F 1H5#+ H߾H1F 1H5B* H߾H1iF 1H5* H pHHI14F 1H5* H YHHI1E H51k* H HHcI1E 1H56* H HH.I1E 1H5* H mHHI1`E 1H5r) H LHHI1+E 1H5]) H߾H1E 1H5p) H HHhI1D 1H5;) H HH3I1D 1H5) H HHI1eD H51( H߾H1>D 1H5( H HHI1 D 1H5u( H HHmI1C 1H5ε@( H sHH8I1C 1H5 ( H߾H1xC 1H5*' H߾H1QC HٺH=K H޿ a7 1H5[' H߾H1C 1H5n' H߾H1B 1H5G' H߾H1B 1H5n ' H߾H1B H߾1H lHboB 1H5& H߾H1HB H߾1H H-*B H߾1H H B 1H5x& H H߾H1A 1H5XJ& H߾H1A Hٺ#H=ӹI 1H5 & H߾H1vA HٺH=I 1H5n% H߾H15A 1H5% H FHHI1A 1H5,l% H 4HHdI1@ 1H5u7% H HH/I1@ 1H5h% H߾H IH1a@ H޿ 4 fD$ LfD==1H5|$ HH1? 1H5%_$ HH1? 1H58$ HH1? HٺH=&G 1H5# HH1d? 1H5&# HHH16? 1H5# HӫHH1? 1H5Pt# HͫHH1> 1H5F# HǫHH1> 1H5J# H aHIH\1w> 1H5" HHH1I> 1H51" HHH1> 1H5" H HIH1= 1H5 R" H XHIH1= 1H5/1" H HIHa1|= 1H5f! H HIH,1G= H޿ q1 1HCommit_0HCommit_2HHCommit_1H5FH HH_1_or_2HƅƅƅH&E! HH1< 1H5! HH1< 1H5E LHLH1Z< 1H54 HH13< 1H5m HH1 < 1H5x HH1; 1H5vQ H HIHA1; 1H5L H JHIH 1{; 1H5 H HIH1F; 1H5 H HIH1; 1H5} HH1: 1H5KV H HIHF1: 1H5! H >HIH1: 1H5z H HIHܿ1K: 1H5e HH1$: 1H5֬ HH19 HٺH=;B H޿  . 1H5A HH19 1H5h HH19 1H5 HH1`9 1H5 HH199 H1H H9 1H5- HH18 H1H ӵHٿ8 H1H MHʿ8 1H5ڶ$ HH18 H1H Hs8 1H5 H \HH1E8 H51 HH18 HپH=\@ H5H]LeLmLuL}I( fH 5 HE1AH1HHff.UHAUATISH&u1{H&MA1Ht41Mu]D1AH\&Ht7HH%s/binCan't find location of %s /tmp/.gprofngLinksunknown expression PROFDATA_TYPE_HWC_DSPACEPROFDATA_TYPE_HWC_GENERALL_CP_TOTALL_CP_TOTAL_CPUPROFDATA_TYPE_STATICPROFDATA_TYPE_OTHERfound != NULLExperiment DurationSECONDSPROFDATA_TYPE_DURATIONPROFDATA_TYPE_GCDURATIONXXX Total Thread TimeXXX Total CPU TimeDerived and Other MetricsMemoryspace Hardware CountersGeneral Hardware CountersStaticCannot open file %sCannot read file %sNot a class file: %s%08llx: _w Invalid opcode%ld to %ld: default=0x%llx%d: default=0x%llxfloatcharshortbytebooleanBOGUS TYPEclass #%u, %u) dim #%d SourceFileInnerClassesCodeLineNumberTablemethod name[%d] is NULL method signature[%d] is NULL %s.%sapp_commentqNTICK_USECMSTATE==%dOMPSTATE==%dPC Addresstotalcpu(MSTATE!=%d)&&(MSTATE!=%d)kcpuLWPID==1masterthreadText Page Fault TimetextpfaultData Page Fault TimedatapfaultKernel Page Fault TimekernelpfaultsleepstopOpenMP Overhead TimeompovhdompworkompwaitOpenMP Implicit Barrier TimeompibarOpenMP Explicit Barrier TimeompebarompserlOpenMP Reduction TimeomprducOpenMP Lock Wait Timeomplkwtompctwtompodwt(EVT_TIME)/%lldsyncnheapalloccntHSIZEheapallocbytesheapleakcntHLEAKEDheapleakbytes(IOTYPE==%d)ioreadcntiowritecntioothercntioerrorcnt(IOTYPE==%d)&&IONBYTEioreadbytesiowritebytes(IOTYPE==%d)&&EVT_TIMEioreadtimeiowritetimeioothertimeioerrortimeRCNTraccessdeadlocks((HWCINT*1000000)/FREQ_MHZ)((HWCINT*1000000)/%d)HWCINT****aconst_nulliconst_m1iconst_0iconst_1iconst_2iconst_3iconst_4iconst_5lconst_0lconst_1fconst_0fconst_1fconst_2dconst_0dconst_1bipushsipushldcldc_wldc2_wiloadlloadfloaddloadiload_0iload_1iload_2iload_3lload_0lload_1lload_2lload_3fload_0fload_1fload_2fload_3dload_0dload_1dload_2dload_3aload_0aload_1aload_2aload_3ialoadlaloadfaloaddaloadaaloadbaloadcaloadsaloadistorelstorefstoredstoreistore_0istore_1istore_2istore_3lstore_0lstore_1lstore_2lstore_3fstore_0fstore_1fstore_2fstore_3dstore_0dstore_1dstore_2dstore_3astore_0astore_1astore_2astore_3iastorelastorefastoredastoreaastorebastorecastoresastorepoppop2dupdup_x1dup_x2dup2dup2_x1dup2_x2swapiaddladdfadddaddisublsubfsubdsubimullmulfmuldmulidivldivfdivddiviremlremfremdremineglnegfnegdnegishllshlishrlshriushrlushriandlandiorlorixorlxoriinci2li2fi2dl2il2fl2df2if2lf2dd2id2ld2fi2bi2ci2slcmpfcmplfcmpgdcmpldcmpgifeqifneifltifgeifgtifleif_icmpeqif_icmpneif_icmpltif_icmpgeif_icmpgtif_icmpleif_acmpeqif_acmpnegotojsrtableswitchlookupswitchireturnlreturnfreturndreturnareturngetstaticputstaticgetfieldputfieldinvokevirtualinvokespecialinvokestaticinvokeinterfaceinvokedynamicnewarraylengthathrowcheckcastinstanceofmonitorentermonitorexitwidemultianewarrayifnullifnonnullgoto_wjsr_wbreakpoint.javacommand badcommand ambiguousInvalid argument to commandinvalid command %c%%-%ds %%s set a new list of metricsdisplay I/O statistics reportdump race access eventsdump mpi messagesdump mpi function callsdump mpi trace eventssend process p signal sdisplay deadlock eventsset a new list of samplesset a new list of threadsset a new list of LWPsdisplay the list of CPUsset a new list of CPUsdisplay processing statisticsadd experiment or groupdrop experimentterminate processing and exitset default visible tabs $display list of index objectsdump pathtree node tabledump PCsdump load-object mapdump threads, lwps, cpusdump clock profile eventsdump IO trace eventsdump HWC profile eventsdump heap trace eventsset a new list of segmentsdefine a filter Commands that list metrics: Miscellaneous commands: Default-setting commands: Unsupported commands: Help command:CCM_MODDATECCM_COMPVERComponent %s, version %sCCM_COMPDATECompilation date %sCCM_COMPOPTCCM_ACOMPOPTActual Compilation options %sCCM_VAR_ALIASVariable %s aliased to %sCCM_FBIRDIFFCCM_OPTRED_SWAPCCM_OPTRED_CPLXCCM_UNKNOWNCCM_UNPAR_CALLCCM_PAR_SERCCM_PAR_SER_VERCCM_PAR_DRECTVCCM_APARLoop below autoparallelizedCCM_AUTOPARCCM_UNPAR_DDCCM_UNPAR_DDACCM_UNPAR_ANONDDCCM_UNPAR_ANONDDACCM_PAR_WORKCCM_UNPAR_EXITCCM_UNPAR_STRNGCCM_UNPAR_IOCCM_PAR_BODY_NAMECCM_UNPAR_NLOOPIDXCCM_UNPAR_DRECTVCCM_UNPAR_NOTPROFITCCM_UNPAR_NESTCCM_UNPARLoop below not parallelizedCCM_UNPAR_NOAUTOCCM_PR_L_VARCCM_SH_L_VARCCM_TP_L_VARCCM_RV_L_VARCCM_IM_L_VARCCM_PR_O_VARCCM_SH_O_VARCCM_TP_O_VARCCM_RV_O_VARCCM_IM_O_VARCCM_UNPAR_IN_OMPCCM_FP_O_VARCCM_LP_O_VARCCM_CP_O_VARCCM_PR_OAS_VARCCM_SH_OAS_VARCCM_FP_OAS_VARCCM_LP_OAS_VARCCM_RV_OAS_VARCCM_FAIL_OAS_VARCCM_SERIALIZE_OASCCM_UNPAR_CALL_2CCM_PAR_DRECTV_2CCM_APAR_2%s autoparallelizedCCM_AUTOPAR_2CCM_UNPAR_DD_2CCM_UNPAR_DDA_2CCM_UNPAR_ANONDD_2CCM_UNPAR_ANONDDA_2CCM_PAR_WORK_2CCM_UNPAR_EXIT_2CCM_UNPAR_STRANGE_2CCM_UNPAR_IO_2CCM_PAR_BODY_NAME_2CCM_UNPAR_NLOOPIDX_2CCM_UNPAR_DRECTV_2CCM_UNPAR_NOTPROFIT_2CCM_UNPAR_NEST_2CCM_UNPAR_2%s not parallelizedCCM_UNPAR_NOAUTO_2CCM_PR_L_VAR_2Private variables in %s: %sCCM_SH_L_VAR_2Shared variables in %s: %sCCM_TP_L_VAR_2CCM_RV_L_VAR_2CCM_IM_L_VAR_2Implicit variables in %s: %sCCM_PR_O_VAR_2CCM_SH_O_VAR_2CCM_TP_O_VAR_2CCM_RV_O_VAR_2CCM_IM_O_VAR_2CCM_UNPAR_IN_OMP_2CCM_FP_O_VAR_2CCM_LP_O_VAR_2CCM_CP_O_VAR_2CCM_PR_OAS_VAR_2CCM_SH_OAS_VAR_2CCM_FP_OAS_VAR_2CCM_LP_OAS_VAR_2CCM_RV_OAS_VAR_2CCM_FAIL_OAS_VAR_2CCM_SERIALIZE_OAS_2CCM_QPERMVECCCM_QEXPRIs expression %s true for %s?CCM_QSAFECALLCCM_LCOSTCCM_UNROLLLoop below unrolled %d timesCCM_IMIXCCM_SPILLSCCM_LFISSIONCCM_LPEELCCM_LBLOCKEDCCM_LTILEDCCM_LUNRJAMCCM_LWHILE2DOCCM_L2CALLCCM_LDEADCCM_LINTRCHNGCCM_FUSEDTOCCM_FUSEDFROMCCM_VECINTRNSCCCM_LSTRIPMINELoop below strip-minedCCM_LNEST2LOOPSCCM_LREVERSECCM_IMIX2CCM_LUNRFULLLoop below fully unrolledCCM_ELIM_NOAMORTINSTCCM_COMP_DALIGNCCM_INTIMIXCCM_LMULTI_VERSIONCCM_LCOST_2CCM_UNROLL_2%s unrolled %d timesCCM_IMIX_BCCM_SPILLS_2CCM_LFISSION_2CCM_LFISSION_FRAGCCM_LPEEL_2CCM_LBLOCKED_2CCM_LOUTER_UNROLLCCM_LJAMMEDCCM_LWHILE2DO_2CCM_L2CALL_2%s replaced by a call to %sCCM_LDEAD_2%s deleted as dead codeCCM_LINTRCHNG_2%s interchanged with %sCCM_LINTRCHNG_ORDERCCM_FUSED_2%s fused with %s, new loop %sCCM_VECINTRNSC_2CCM_LSTRIPMINE_2CCM_LNEST2LOOPS_2CCM_LREVERSE_2CCM_IMIX2_BCCM_LUNRFULL_2%s fully unrolledCCM_ELIM_NOAMORTINST_2CCM_COMP_DALIGN_2CCM_INTIMIX_2CCM_OMP_REGIONCCM_LMICROVECTORIZE%s is micro-vectorizedCCM_LMULTI_VERSION_2CCM_LCLONEDCCM_LUNSWITCHEDCCM_LRESWITCHEDCCM_LSKEWBLOCKEDCCM_IVSUBCCM_ONEITER_REPLACEDCCM_IMIX3_BCCM_PIPELINELoop below pipelinedCCM_PIPESTATSCCM_NOPIPE_CALLCCM_NOPIPE_INTCCCCM_NOPIPE_MBARCCM_NOPIPE_MNMXCCM_NOPIPE_U2FLTCCM_NOPIPE_GOTCCM_NOPIPE_IDIVCCM_NOPIPE_PRFTCHCCM_NOPIPE_EXITCCM_NOPIPE_REGCCM_NOPIPE_UNSCCM_NOPIPE_UNSUITCCM_NOPIPE_INTRINSICCCM_NOPIPE_BIGCCM_NOPIPE_INVINTPRCCM_NOPIPE_INVFLTPRCCM_NOPIPE_INVDBLPRCCM_PIPE_SCHEDAFIPRCCM_PIPE_SCHEDAFDPRCCM_PIPE_SCHEDAFFPRCCM_NOPIPE_INTPRCCM_NOPIPE_DBLPRCCM_NOPIPE_FLTPRCCM_PIPELINE_2%s pipelinedCCM_PIPESTATS_2CCM_NOPIPE_CALL_2CCM_NOPIPE_INTCC_2CCM_NOPIPE_MBAR_2CCM_NOPIPE_MNMX_2CCM_NOPIPE_U2FLT_2CCM_NOPIPE_GOT_2CCM_NOPIPE_IDIV_2CCM_NOPIPE_PRFTCH_2CCM_NOPIPE_EXIT_2CCM_NOPIPE_REG_2CCM_NOPIPE_UNS_2CCM_NOPIPE_UNSUIT_2CCM_NOPIPE_INTRINSIC_2CCM_NOPIPE_BIG_2CCM_NOPIPE_INVINTPR_2CCM_NOPIPE_INVFLTPR_2CCM_NOPIPE_INVDBLPR_2CCM_PIPE_SCHEDAFIPR_2CCM_PIPE_SCHEDAFDPR_2CCM_PIPE_SCHEDAFFPR_2CCM_NOPIPE_INTPR_2CCM_NOPIPE_DBLPR_2CCM_NOPIPE_FLTPR_2CCM_INLINECCM_INLINE2CCM_INLINE_TMPLTCCM_INLINE_TMPLT2CCM_INLINE_OUT_COPYCCM_NINLINE_RECCCM_NINLINE_NESTCCM_NINLINE_CMPLXCCM_NINLINE_FBCCM_NINLINE_PARCCM_NINLINE_OPTCCM_NINLINE_USRCCM_NINLINE_AUTOCCM_NINLINE_CALLSCCM_NINLINE_ACTUALCCM_NINLINE_FORMALCCM_NINLINE_TYPECCM_NINLINE_ATYPECCM_NINLINE_RETTYPECCM_NINLINE_EXCPTCCM_NINLINE_UNSAFECCM_NINLINE_ALIASCCM_NINLINE_FEMARKCCM_NINLINE_RAREXCCM_CLONINGCCM_INLINE_BCCM_INLINE2_BCCM_INLINE_LOOPCCM_NINLINE_MULTIENTRYCCM_NINLINE_VARARGSCCM_NINLINE_UNSEEN_BODYCCM_NINLINE_UPLEVELCCM_NINLINE_CMDLINECCM_NINLINE_CALL_CMPLXCCM_NINLINE_LANG_MISMATCHCCM_NINLINE_RTN_WEAKCCM_NINLINE_CALL_WEAKFILECCM_NINLINE_CALL_TRYCATCHCCM_NINLINE_CALL_REGPCCM_NINLINE_RTN_REGPCCM_NINLINE_CALL_XPENSVCCM_NINLINE_READONLYIRCCM_NINLINE_CALL_THUNKCCM_NINLINE_CALL_XTARGETSCCM_NINLINE_PRAGMACCM_NINLINE_CMPLX2CCM_NINLINE_RARECCM_NINLINE_PAR2CCM_NINLINE_G_LIMITCCM_NINLINE_L_LIMITCCM_NINLINE_REC2CCM_NINLINE_FB2CCM_NINLINE_CS_CMPLXCCM_NINLINE_R_EXCPTCCM_NINLINE_ASMCCM_NINLINE_R_READONLYIRCCM_NINLINE_C_READONLYIRCCM_NINLINE_NEVERRETURNCCM_MPREFETCHPrefetch of %s insertedCCM_MPREFETCH_LDCCM_MPREFETCH_STCCM_MPREFETCH_FBCCM_MPREFETCH_FB_LDCCM_MPREFETCH_FB_STCCM_MLOADLoad below refers to %sCCM_MSTOREStore below refers to %sCCM_MLOAD_PCCM_MSTORE_PCCM_COPYINCCM_COPYOUTCCM_COPYINOUTCCM_PADDINGCCM_PADCOMMONCCM_ALIGN_EQCCM_ALIGN_PERFCCM_ALIGN_STRUCTCCM_TMP_COPYCCM_TMP_COPYMCCM_PROC_MISMATCHCCM_PROC_MISMATCH2CCM_PROC_MISMATCH3CCM_DO_EXPRCCM_AUTO_BNDCCM_LIT_PADCCM_ARRAY_LOOPCCM_ARRAY_LOOPNESTCCM_ALIGN_PERF2CCM_ALIGN_PERF3CCM_IO_LOOP_ARRAYCCM_TMPCONSTCCM_TMPDESTCCM_DBL_CONSTCCM_MINLINECCM_MINLINE2CCM_MINLINE3CCM_MINLINE4CCM_TMP_COPYOUTCCM_TMP_COPYOUTMCCM_TMP_COPYINOUTCCM_TMP_COPYINOUTMCCM_ARRAY_LOOP_2CCM_ARRAY_LOOPNEST_2CCM_IO_LOOP_ARRAY_2CCM_USER_LOOPSource loop below has tag %sCCM_FOUND_LOOPCCM_MFUNCTION_LOOPCCM_FSIMPLECCM_STACKCCM_TAILRECURCCM_TAILCALLCCM_NI_EXIT_OR_PSEUDOCCM_NI_BAD_UNARY_OPCCCM_NI_INT_LDD_ON_V9CCM_NI_LATE_INL_OPCCCM_NI_BAD_IMM_OPCCM_NI_BAD_STATELEAFCCM_NI_BAD_ASR_19CCM_NI_BAD_FSR_USECCM_NI_BAD_REGISTERCCM_NI_NO_RET_VALCCM_NI_DELAYCCM_NI_SCALLCCM_CASE_POSITIONCCM_CALL_WITH_CODECCM_NI_BAD_SP_ADDRCCM_NI_BAD_SP_USAGECCM_NI_MIXED_REG_TYPES-version-help-whoami=functionsmetric_specfsummaryfsinglefunction_name #callers-calleesgprofcsinglecprependcappendcrmfirstcrmlastcalltreectreeallocsheapstatioactivityiodetailiocallstackiostatpcspsummarylsummarysourcefunc/file #disasmscccom_specsthreshdccdthreshsetpathpath_listaddpathpathmapold_prefix new_prefixpreload_libdirsindxobjindxobj_listindxobj_definetype "index-expr"dsummary{deadlock_id|all}experiment_listexp_listsample_listlwp_listthread_listcpu_listfiltersfilter-specificationdescribesample_selectsample_speclwp_selectlwp_specthread_selectthread_speccpu_selectcpu_specobject_listobject_showobj1,...object_hideobject_apiobjects_defaultobject_selectcmetric_listgmetric_listindx_metric_listoutfilefilenameappendfileviewmode{user|expert|machine}compare{on|off|delta|ratio}printmodeexp_idoverviewsample_detailopen_expadd_expdrop_expdmetricsdsorten_desc{on|off|=}tlmodetl_modetldatatl_datatabstablistcallflametimelinesrcdisifreqprocstatsscriptdfuncsddobjsdnodesdstacksdunkpcdmapdentitiesignore_no_xhwcprofignore_fs_warndprofiledsyncdiotracedhwcdheapr_accsdmpi_funcsdmpi_msgsdmpi_eventsdmemdumpgcdkillxquitxhelpwhoamipmapsegment_listsegment_selectseg1,....jar.zipindex <= countAvailable name list: %8d) Cancel %8d) %s %8d) %s %s:0x%llx %8d) %s %s:0x%llx (%s) %8d) %s(%s) Enter selection: %c%+6lld %sNO_TYPE%c%+6lld .{%s %s} .%s%s.{%s %s}ORPHAN/bin/rm -rf %s/tmp/analyzer.%llu.%lldindex >= 0OK#analyzer experiment groupCannot create file %s (%s)1.3.2%s: inflateInit2 failed (%s)Cannot open file `%s'No files in %szip:jar:file:jdynclasses%s/%s/%s%s (not found)%s (found as %s)$exptsindex < countDefault selection "1" made 0x%016llxHWCDOBJConstructing MetricsCan not drop subexperiments/bin/rm -rf data.frameinfoGroup %d.ergATSTAMPETSTAMPTHRIDLWPIDCPUIDFRINFOSMPLOBJGCEVENTOBJVOIDP_OBJUCPUSCPUTFLTDFLTKFLTULCKTSLPWCPUMSTATENTICKOMPSTATESRQSTSOBJHWCTAGPADDRVIRTPCPHYSPCLWP_LGRP_HOMEPS_LGRP_HOMEEA_PAGESIZEEA_LGRPPC_PAGESIZEPC_LGRPMEM_LATMEM_SRCHTYPEHVADDRHOVADDRLeaked bytesHMEM_USAGEFreed bytesHFREEDCurrent allocationsHCUR_ALLOCSHCUR_NET_ALLOCCurrent leaksHCUR_LEAKSDDSCR_LNKIOTYPEIOFDIORQSTIOOFDIOFNAMEIOFSTYPECPRIDPPRIDPTSKIDPRPCRTYPELEAFPCRVADDRDIDDLTYPEDVADDRMSTACKUSTACKXSTACKHSTACKSTACKIDJava thread numberJTHREADSAMPLE_MAPGCEVENT_MAPProcess idExperiment idEXPIDComparable Experiment IdEXPID_CMPComparison Group idEXPGRIDPARREGStart Timestamp (nanoseconds)TSTAMP_LOEnd Timestamp (nanoseconds)TSTAMP_HITSTAMP2CPU Frequency, MHzFREQ_MHZIOHEAPBYTESMSTACKLUSTACKLXSTACKLMSTACKIUSTACKIXSTACKI(unknown)((EXPID_CMP<<%llu) | THRID)(CPUID)Samples(SAMPLE_MAP)GCEvents(GCEVENT_MAP)Seconds(TSTAMP/1000000000)Processes(EXPID_CMP)Experiment_IDsDatasize-IPC-DIPCt%s%s Time(Padding in structure)(No type information)(OK)(UNKNOWN) Master list of DataObjects: id %6lld: [%4lld] %s master=%lld master=?? MASTER UINT32UINT64BOOLENUMFK_LABELLabelsFK_EVTPROPMisc. DefinitionsFK_IDXOBJIndex Object DefinitionsGPROFNG_DBE_NTHREADSMAIN_Segment %d -- %s -- %s Experiment %d -- %s ^%s$%2d %s cycles/instsinsts/cyclesK_cycles/K_instsKernel Cycles Per InstructionK_CPIK_insts/K_cyclesKernel Instructions Per CycleK_IPCEXPGRID==%dindex == dataViews->size ()ei.user:nameUnable to open fileData corrupted(unnamed)%s [%s] = %s [%s] / %s [%s] cannot eval NULL expression %%%dllx: DW_TAG_array_typeDW_TAG_entry_pointDW_TAG_enumeration_typeDW_TAG_formal_parameterDW_TAG_imported_declarationDW_TAG_labelDW_TAG_lexical_blockDW_TAG_memberDW_TAG_pointer_typeDW_TAG_reference_typeDW_TAG_compile_unitDW_TAG_string_typeDW_TAG_structure_typeDW_TAG_subroutine_typeDW_TAG_typedefDW_TAG_union_typeDW_TAG_unspecified_parametersDW_TAG_variantDW_TAG_common_blockDW_TAG_common_inclusionDW_TAG_inheritanceDW_TAG_inlined_subroutineDW_TAG_moduleDW_TAG_ptr_to_member_typeDW_TAG_set_typeDW_TAG_subrange_typeDW_TAG_with_stmtDW_TAG_access_declarationDW_TAG_base_typeDW_TAG_catch_blockDW_TAG_const_typeDW_TAG_constantDW_TAG_enumeratorDW_TAG_file_typeDW_TAG_friendDW_TAG_namelistDW_TAG_namelist_itemDW_TAG_packed_typeDW_TAG_subprogramDW_TAG_template_type_paramDW_TAG_template_value_paramDW_TAG_thrown_typeDW_TAG_try_blockDW_TAG_variant_partDW_TAG_variableDW_TAG_volatile_typeDW_TAG_dwarf_procedureDW_TAG_restrict_typeDW_TAG_interface_typeDW_TAG_namespaceDW_TAG_imported_moduleDW_TAG_unspecified_typeDW_TAG_partial_unitDW_TAG_imported_unitDW_TAG_lo_userDW_TAG_MIPS_loopDW_TAG_format_labelDW_TAG_function_templateDW_TAG_class_templateDW_TAG_GNU_BINCLDW_TAG_GNU_EINCLDW_TAG_GNU_call_siteDW_TAG_SUN_codeflagsDW_TAG_SUN_memop_infoDW_TAG_hi_userDW_TAG_icc_compile_unitDW_TAG_rvalue_reference_typeDW_TAG_coarray_typeDW_TAG_generic_subrangeDW_TAG_dynamic_typeDW_TAG_atomic_typeDW_TAG_call_siteDW_TAG_call_site_parameterDW_TAG_skeleton_unitDW_TAG_immutable_typeDW_TAG_class_typeDW_AT_siblingDW_AT_nameDW_AT_orderingDW_AT_subscr_dataDW_AT_byte_sizeDW_AT_bit_offsetDW_AT_bit_sizeDW_AT_element_listDW_AT_stmt_listDW_AT_low_pcDW_AT_high_pcDW_AT_languageDW_AT_memberDW_AT_discrDW_AT_discr_valueDW_AT_visibilityDW_AT_importDW_AT_string_lengthDW_AT_common_referenceDW_AT_comp_dirDW_AT_const_valueDW_AT_containing_typeDW_AT_default_valueDW_AT_inlineDW_AT_is_optionalDW_AT_lower_boundDW_AT_producerDW_AT_prototypedDW_AT_return_addrDW_AT_start_scopeDW_AT_stride_sizeDW_AT_upper_boundDW_AT_abstract_originDW_AT_accessibilityDW_AT_address_classDW_AT_artificialDW_AT_base_typesDW_AT_calling_conventionDW_AT_countDW_AT_data_member_locationDW_AT_decl_columnDW_AT_decl_fileDW_AT_decl_lineDW_AT_declarationDW_AT_discr_listDW_AT_encodingDW_AT_externalDW_AT_frame_baseDW_AT_friendDW_AT_identifier_caseDW_AT_macro_infoDW_AT_namelist_itemDW_AT_priorityDW_AT_segmentDW_AT_specificationDW_AT_static_linkDW_AT_typeDW_AT_use_locationDW_AT_variable_parameterDW_AT_virtualityDW_AT_vtable_elem_locationDW_AT_allocatedDW_AT_associatedDW_AT_data_locationDW_AT_byte_strideDW_AT_entry_pcDW_AT_use_UTF8DW_AT_extensionDW_AT_rangesDW_AT_trampolineDW_AT_call_columnDW_AT_call_fileDW_AT_call_lineDW_AT_descriptionDW_AT_binary_scaleDW_AT_decimal_scaleDW_AT_smallDW_AT_decimal_signDW_AT_digit_countDW_AT_picture_stringDW_AT_mutableDW_AT_threads_scaledDW_AT_explicitDW_AT_object_pointerDW_AT_endianityDW_AT_elementalDW_AT_pureDW_AT_recursiveDW_AT_signatureDW_AT_main_subprogramDW_AT_data_bit_offsetDW_AT_const_exprDW_AT_enum_classDW_AT_linkage_nameDW_AT_lo_userDW_AT_MIPS_fdeDW_AT_MIPS_loop_beginDW_AT_MIPS_tail_loop_beginDW_AT_MIPS_epilog_beginDW_AT_MIPS_loop_unroll_factorDW_AT_MIPS_linkage_nameDW_AT_MIPS_strideDW_AT_MIPS_abstract_nameDW_AT_MIPS_clone_originDW_AT_MIPS_has_inlinesDW_AT_sf_namesDW_AT_src_infoDW_AT_mac_infoDW_AT_src_coordsDW_AT_body_beginDW_AT_body_endDW_AT_GNU_vectorDW_AT_GNU_guarded_byDW_AT_GNU_pt_guarded_byDW_AT_GNU_guardedDW_AT_GNU_pt_guardedDW_AT_GNU_locks_excludedDW_AT_GNU_odr_signatureDW_AT_GNU_template_nameDW_AT_GNU_call_site_valueDW_AT_GNU_call_site_targetDW_AT_GNU_tail_callDW_AT_GNU_all_tail_call_sitesDW_AT_GNU_all_call_sitesDW_AT_GNU_locviewsDW_AT_GNU_entry_viewDW_AT_SUN_command_lineDW_AT_SUN_func_offsetsDW_AT_SUN_cf_kindDW_AT_SUN_func_offsetDW_AT_SUN_memop_type_refDW_AT_SUN_profile_idDW_AT_SUN_memop_signatureDW_AT_SUN_obj_dirDW_AT_SUN_obj_fileDW_AT_SUN_original_nameDW_AT_SUN_link_nameDW_AT_hi_userDW_AT_icc_flagsDW_AT_string_length_bit_sizeDW_AT_string_length_byte_sizeDW_AT_rankDW_AT_str_offsets_baseDW_AT_addr_baseDW_AT_rnglists_baseDW_AT_dwo_nameDW_AT_referenceDW_AT_rvalue_referenceDW_AT_macrosDW_AT_call_all_callsDW_AT_call_all_source_callsDW_AT_call_all_tail_callsDW_AT_call_return_pcDW_AT_call_valueDW_AT_call_originDW_AT_call_parameterDW_AT_call_pcDW_AT_call_tail_callDW_AT_call_targetDW_AT_call_target_clobberedDW_AT_call_data_locationDW_AT_call_data_valueDW_AT_noreturnDW_AT_alignmentDW_AT_export_symbolsDW_AT_deletedDW_AT_defaultedDW_AT_loclists_baseDW_AT_locationDW_FORM_addrDW_FORM_block4DW_FORM_data2DW_FORM_data4DW_FORM_data8DW_FORM_data16DW_FORM_line_strpDW_FORM_implicit_constDW_FORM_stringDW_FORM_blockDW_FORM_block1DW_FORM_data1DW_FORM_flagDW_FORM_sdataDW_FORM_strpDW_FORM_udataDW_FORM_ref_addrDW_FORM_GNU_ref_altDW_FORM_GNU_strp_altDW_FORM_ref1DW_FORM_ref2DW_FORM_ref4DW_FORM_ref8DW_FORM_ref_udataDW_FORM_indirectDW_FORM_sec_offsetDW_FORM_exprlocDW_FORM_flag_presentDW_FORM_ref_sig8DW_FORM_block2DW_LNCT_pathDW_LNCT_timestampDW_LNCT_sizeDW_LNCT_MD5DW_LNCT_lo_userDW_LNCT_hi_userDW_LNCT_directory_indexEXPGRID==1%sunspecified:enumeration:%s=%sconst+volatile+pointer+reference+array[%lld]:%sarray[]:%sstructure:union:class:%s:%lldUndefined: || EXPID>= && EXPID<=.%c0x%llx [ 0x%llx ]%s [ 0x%llx, .%c0x%llx].debug_info.debug_abbrev.debug_str.debug_line.debug_ranges.debug_line_str%.*s.%s_bm1 != NULLLINUX_CPUUnexpected mstate = %d %s [0x%016llx] ReadTraceWriteTraceOpenTraceCloseTraceOtherIOTraceReadTraceErrorWriteTraceErrorOpenTraceErrorCloseTraceErrorOtherIOTraceErrorUnknownIOTraceType $$mallocfreereallocmmapmunmap(EXPID== && ())%s %-21s %02x dwrCUs[%lld]: %s:%s .debug_rnglistsDwarf::get_debug_rnglistsdir_namesfile_namesDW_RLE_end_of_listDW_RLE_base_addressDW_RLE_start_lengthDW_RLE_offset_pairDW_RLE_start_endDW_RLE_base_addressxDW_RLE_startx_endxDW_RLE_startx_length*** Collector Warning*** Collector Error*** Collector Fatal ErrorComment*** Log Error*** Archive Error*** Internal Error%s: No error%s: Data argument too long%s: Can't open overview %s%s: Can't write overview %s%s: Open failed %s%s: Mmap failed %s%s: Can't open map file `%s'%s: Can't read map file `%s'%s: Can't write map file%s: Initializing RDT failed%s: General error%s: Exec of process failed%s: Failure to open log file%s: No warning%s: Long fstat call -- %s%s: Long read call -- %sArgument list `%s'Mayas snap file `%s'Target fork: %sTarget exec: %sTarget fork/exec: %sFox snap file `%s'Rock simulator snap file `%s'Bit instrument data file `%s'Bit snap file `%s'*** Collect: %s%s: Number %d ("%s")DwrCU::get_ranges:UnnamedUnitDwrCU::get_symbols:.stab.stabstr.stab.index.stab.indexstr.stab.excl.stab.exclstr.__analyzer_info.info.plt.debugMALLOCFREEREALLOCMMAPMUNMAPOPENCLOSEOTHERIOREADERRORWRITEERROROPENERRORCLOSEERROROTHERIOERRORReadWriteOpenCloseOther I/ORead errorWrite errorOpen errorClose errorOther I/O error.SUNW_ancillaryELFCLASSNONEELFCLASS32ELFCLASS_UNKNOWNELFCLASS64ELFDATANONEELFDATA2LSBELFDATA_UNKNOWNELFDATA2MSBELFOSABI_UNKNOWNELFOSABI_NONEELFOSABI_HPUXELFOSABI_NETBSDELFOSABI_LINUXELFOSABI_SOLARISELFOSABI_AIXELFOSABI_IRIXELFOSABI_FREEBSDELFOSABI_TRU64ELFOSABI_MODESTOELFOSABI_OPENBSDETYPE_UNKNOWNET_HIPROCET_RELET_EXECET_DYNET_COREET_LOPROCET_NONEELFMACHINE_UNKNOWNEM_XTENSAEM_M32EM_SPARCEM_386EM_68KEM_88KEM_860EM_MIPSEM_S370EM_MIPS_RS3_LEEM_SPARC32PLUSEM_960EM_PPCEM_PPC64EM_V800EM_FR20EM_RH32EM_RCEEM_ARMEM_ALPHAEM_SHEM_SPARCV9EM_TRICOREEM_ARCEM_H8_300EM_H8_300HEM_H8SEM_H8_500EM_IA_64EM_MIPS_XEM_COLDFIREEM_68HC12EM_MMAEM_PCPEM_NCPUEM_NDR1EM_STARCOREEM_ME16EM_ST100EM_TINYJEM_X86_64EM_PDSPEM_FX66EM_ST9PLUSEM_ST7EM_68HC16EM_68HC11EM_68HC08EM_68HC05EM_SVXEM_ST19EM_VAXEM_CRISEM_JAVELINEM_FIREPATHEM_ZSPEM_MMIXEM_HUANYEM_PRISMEM_AVREM_FR30EM_D10VEM_D30VEM_V850EM_M32REM_MN10300EM_MN10200EM_PJEM_OPENRISCEM_NONEEV_NONEVERSION_UNKNOWNEV_CURRENTPTYPE_UNKNOWNPT_HIPROCPT_LOADPT_DYNAMICPT_INTERPPT_NOTEPT_SHLIBPT_PHDRPT_TLSPT_LOOSPT_GNU_EH_FRAMEPT_HIOSPT_LOPROCPT_NULLSHTYPE_UNKNOWNSHT_HIUSERSHT_PROGBITSSHT_SYMTABSHT_STRTABSHT_RELASHT_HASHSHT_DYNAMICSHT_NOTESHT_NOBITSSHT_RELSHT_SHLIBSHT_DYNSYMSHT_INIT_ARRAYSHT_FINI_ARRAYSHT_PREINIT_ARRAYSHT_GROUPSHT_SYMTAB_SHNDXSHT_LOOSSHT_SUNW_verdefSHT_HIOSSHT_SUNW_verneedSHT_LOPROCSHT_HIPROCSHT_LOUSERSHT_NULLANCILLARY_TAG_UNKNOWNANC_SUNW_NULLANC_SUNW_CHECKSUMANC_SUNW_MEMBERANC_SUNW_NUMELF Header: %s Cannot read Elf header e_ident %-15s %xEI_CLASS %-15s %10lld ( %s ) EI_DATAEI_OSABIe_machinee_versione_entry %-15s 0x%08llx ( %lld ) e_phoffe_shoffe_flagse_ehsizee_phentsizee_phnume_shentsizee_shnume_shstrndx Program Header[%d]: p_typep_flags %-15s 0x%08llx [PF_XPF_WPF_RPF_MASKPROCp_offsetp_vaddrp_paddrp_fileszp_memszp_align Section Header[%d]: sh_namesh_typesh_flagsSHF_WRITESHF_ALLOCSHF_EXECINSTRSHF_MERGESHF_STRINGSSHF_INFO_LINKSHF_LINK_ORDERSHF_OS_NONCONFORMINGSHF_GROUPSHF_TLSSHF_SUNW_ABSENTSHF_EXCLUDEsh_addrsh_offsetsh_sizesh_linksh_infosh_addralignsh_entsize Section[%d]: %s %10d %-20s 0x%08llx %6lldcollectorsettingblkszstackbasehwc_defaultnoidlefaketimedelay_startterminatepause_signalsample_periodsample_signalsearch_pathSearch path: %slinetracecollenvXXX %s = %s hostnameSunOSarchi86pci686x86_64aarch64riscv64bigendianpagesznpagespowermfrequencyfrequency_scalingturbo_modeprocesswsizeppidpgrpsidcwdtstamparchive_rungprofng-archive run: XXXXXXXsamplecerrorcwarncomment*** Note: %sdesc_startlineagefollowmsgdesc_startedexec_startexec_errorjthread_startgrpnameprntnametidjthrjenvjthread_endgc_endgc_startPause: %ld.%09ldPause (%s): %ld.%09ldResume: %ld.%09ldthread_pauseThread %llu pause: %ld.%09ldthread_resumeThread %llu resume: %ld.%09ldfoffsetmodeschksumobjectLinuxKernelfunctiondynfuncDYNAMIC_FUNCTIONSfuncnamejcmmethodIdnumstatesptimerText Page FaultData Page FaultUser+System CPUThread stateNumber of Profiling Ticksheaptracesynctracethresholdomptracehwcountercpuverhwcnameint_nameintervalmemopmodstrhwsimctrmetricreg_numtimecvtdversionjprofilejversiondataraceschemedeadlockdataptrprofdatafnamehwcountersprofpcktformatunamenoshowdtracefatal/usr/lib/debug/usr/lib/debug/usr%.*s%snotes%.*s.class%.*sLoading CallStack Data: %sLoading Race Data: %sdataracesLoading Deadlocks Data: %s%s -- %s%s at line %d, column %drunlogqerrorqnotesqpprocqNotes:OpenMP Parallel RegionOMP_pregOpenMP TaskOMP_taskLoading OpenMP Data: %sifreqqLoading HW Profile Data: %sData collection parameters:Native- and Java-APIsJAVA-APIsNative-APIs Heap tracing IO tracingdual-stacksingle-stackleaf Datarace detection, %s Deadlock detection Periodic sampling, %d secs. Experiment size limit, %d Pause signal %s Sample signal %sExperiment started %s Target command (%s): '%s'64-bit32-bitUser: `%s'Current working directory: %sKernel driver version: `%s'JVM version: `%s' Machine model: %swarnings.xmllog.xmlmap.xmlrelativelbl_tslabels.xmlAfter sortUserLabels:%s %sarchives%s/../%sjclassesarchive file malformed %sEvent durationLoading Profile Data: %sLoading Synctrace Data: %sHigh resolution timestampSample numberGCEvent numberLoading IO Trace Data: %sVirtual File DescriptorN/ALoading Heap Trace Data: %sHeap Memory UsageBytes FreedNet Bytes AllocatedNet Bytes LeakedExperiment %s .er/_%.*s%c%s_%s%s%c%sCopying `%s' to `%s' gprofng-archive: remove %s %s/%u_%s%s/archive_%llxdyntextds != NULLProcessing Dynamic Text: %sMachine Call StackUser Call StackExpert Call StackShowHide Call StackJava ThreadNOIDLEATWTOpenMP stateTSKWTNoneOverheadImplicit BarrierExplicit BarrierIdleSerialReductionLock WaitCritical Section WaitOrdered Section WaitAtomic WaitTask Waittype == TYPE_OBJOpenMP parallel regionOpenMP taskProcessing CallStack Data%s %s: %szfsnfsufsudfslofsvxfstmpfspcfshsfsprocfsfifofsswapfscachefsautofsspecfssockfsfdfsmntfsnamefsobjfssharefsext2ext3ext4LWPgcevent%s (IOVFD=%lld, FD=%d)%s (IOVFD=%lld)%s (FS=%s)(data not recorded)(all)total %lld, range: %lld-%lld(%lld items selected)%s [%s] && nonevoidobj == NULLJava_FUNCTIONMODULELOADOBJECTEADDRINDEXOBJPAGESOURCEFILEEXPERIMENT%s -- cloned version [%s]%s -- outline code [%s]%s, line %u in "%s"Stack 0x%llx(a != (const void *) NULL)(b != (const void *) NULL)xxxxxxxxxxxxxxxxxxxxxxXXXX Threshold XXXX(NULL) Hist_data dump: %s %d=%d metrics %4d %15s %4d %15s HistItem listing %f %12.6lf %12lld %p %12llu%30s%s:%lld <-- %s:%lld %-*s 0. %6.2f %-*s%s + 0x%08X + 0x%016llXagent errorGC activeunknown non-Java frameunwalkable non-Java frameunknown Java frameunwalkable Java frameunknown thread statethread in exitdeopt in process tickssafepoint synchronizing ticksunexpected error<%s (%d)> func=0x%016lx lineno=%lldFK_MEMOBJMemory Object Definitions<%s>Error: unable to open file %sError: unable to map file %s./%s.ermm%s/%s/%s.ermm [save 0x%llx] %s (module = %s) (Source = %s)fp != NULL@0x%llx (%s)Processing Load Object Data@pltMemory_page_size%s 0x%16.16llx (%llu)Memory_in_home_lgrpTrueFalseMemory_lgrp%s %llu%s 0x%16.16llxNo Machine model is loaded Machine model %s not found %s: line %d `%s %s %s' Process %llu, Thread %llu [ Group %llu Process %llu ]%s, Process %3llu, PID %lluProcess %3lluBaselineComparison[%s-%llu]CPU %lluSample %lluNot in any GCEventGCEvent %lluSecond of execution %lluProcess %llu>= %3llu TB%3lluTB < n <= %3lluTB256GB < n <= %3lluTB%3lluGB < n <= %3lluGB256MB < n <= %3lluGB%3lluMB < n <= %3lluMB256KB < n <= %3lluMB%3lluKB < n <= %3lluKB 256 < n <= %3lluKB 1 Byte%5llu < n <= %5llu Bytes 0 Bytesn > 10000s1000s < n <= 10000s 100s < n <= 1000s 10s < n <= 100s 1s < n <= 10s100ms < n <= 1s 10ms < n <= 100ms 1ms < n <= 10ms100us < n <= 1ms 10us < n <= 100us 1us < n <= 10us 0s < n <= 1us 0s%s from %s%s %s (0x%llxlo_warnqlo_commentqCannot find file: `%s'Cannot open ELF file `%s'%s_debug%s_debug_alt%s_altCan't open file: %ssec.deltaratio %*s %%.+%.%.+.-.%-.+%-Exclusive User CPU TimeExcl. User CPUInclusive User CPU TimeIncl. User CPUAttributed User CPU TimeAttr. User CPUExclusive Wait CPU TimeExcl. Wait CPUInclusive Wait CPU TimeIncl. Wait CPUAttributed Wait CPU TimeAttr. Wait CPUExclusive User Lock TimeExcl. User LockInclusive User Lock TimeIncl. User LockAttributed User Lock TimeAttr. User LockExclusive System CPU TimeExcl. Sys. CPUInclusive System CPU TimeIncl. Sys. CPUAttributed System CPU TimeAttr. Sys. CPUExclusive Sync Wait TimeExcl. Sync WaitInclusive Sync Wait TimeIncl. Sync WaitAttributed Sync Wait TimeAttr. Sync WaitExcl. Text FaultIncl. Text FaultAttr. Text FaultExcl. Data FaultIncl. Data FaultAttr. Data FaultExclusive Kernel CPU TimeExcl. Kernel CPUInclusive Kernel CPU TimeIncl. Kernel CPUAttributed Kernel CPU TimeAttr. Kernel CPUExclusive Excl. Inclusive Incl. Attributed Attr. Data-derived Data. Exclusive %sExcl. %sInclusive %sIncl. %sAttributed %sAttr. %sExclusive Master Thread TimeExcl. Master ThreadInclusive Master Thread TimeIncl. Master ThreadAttributed Master Thread TimeAttr. Master ThreadExclusive Total Thread TimeExcl. Total ThreadInclusive Total Thread TimeIncl. Total ThreadAttributed Total Thread TimeAttr. Total ThreadExclusive Sync Wait CountExcl. Sync Wait CountInclusive Sync Wait CountIncl. Sync Wait CountAttributed Sync Wait CountAttr. Sync Wait CountExclusive Total CPU TimeExcl. Total CPUInclusive Total CPU TimeIncl. Total CPUAttributed Total CPU TimeAttr. Total CPUExclusive Trap CPU TimeExcl. Trap CPUInclusive Trap CPU TimeIncl. Trap CPUAttributed Trap CPU TimeAttr. Trap CPUExcl. Kernel Page FaultIncl. Kernel Page FaultAttr. Kernel Page FaultExclusive Sleep TimeExcl. SleepInclusive Sleep TimeIncl. SleepAttributed Sleep TimeAttr. SleepExclusive Stopped TimeExcl. StoppedInclusive Stopped TimeIncl. StoppedAttributed Stopped TimeAttr. StoppedExclusive Bytes AllocatedExcl. Bytes AllocatedInclusive Bytes AllocatedIncl. Bytes AllocatedAttributed Bytes AllocatedAttr. Bytes AllocatedExclusive AllocationsExcl. AllocationsInclusive AllocationsIncl. AllocationsAttributed AllocationsAttr. AllocationsExclusive Bytes LeakedExcl. Bytes LeakedInclusive Bytes LeakedIncl. Bytes LeakedAttributed Bytes LeakedAttr. Bytes LeakedExclusive LeaksExcl. LeaksInclusive LeaksIncl. LeaksAttributed LeaksAttr. LeaksExclusive Read BytesExcl. Read BytesInclusive Read BytesIncl. Read BytesAttributed Read BytesAttr. Read BytesExclusive Write BytesExcl. Write BytesInclusive Write BytesIncl. Write BytesAttributed Write BytesAttr. Write BytesExclusive Read CountExcl. Read CountInclusive Read CountIncl. Read CountAttributed Read CountAttr. Read CountExclusive Write CountExcl. Write CountInclusive Write CountIncl. Write CountAttributed Write CountAttr. Write CountExclusive Other I/O CountExcl. Other I/O CountInclusive Other I/O CountIncl. Other I/O CountAttributed Other I/O CountAttr. Other I/O CountExclusive I/O Error CountExcl. I/O Error CountInclusive I/O Error CountIncl. I/O Error CountAttributed I/O Error CountAttr. I/O Error CountExclusive Read TimeExcl. Read TimeInclusive Read TimeIncl. Read TimeAttributed Read TimeAttr. Read TimeExclusive Write TimeExcl. Write TimeInclusive Write TimeIncl. Write TimeAttributed Write TimeAttr. Write TimeExclusive Other I/O TimeExcl. Other I/O TimeInclusive Other I/O TimeIncl. Other I/O TimeAttributed Other I/O TimeAttr. Other I/O TimeExclusive I/O Error TimeExcl. I/O Error TimeInclusive I/O Error TimeIncl. I/O Error TimeAttributed I/O Error TimeAttr. I/O Error TimePC Addr.Exclusive Non-OpenMP TimeExcl. Non-OMPInclusive Non-OpenMP TimeIncl. Non-OMPAttributed Non-OpenMP TimeAttr. Non-OMPExcl. OMP ovhd.Incl. OMP ovhd.Attr. OMP ovhd.Exclusive OpenMP Work TimeExcl. OMP WorkInclusive OpenMP Work TimeIncl. OMP WorkAttributed OpenMP Work TimeAttr. OMP WorkExcl. OMP i-barr.Incl. OMP i-barr.Attr. OMP i-barr.Excl. OMP e-barr.Incl. OMP e-barr.Attr. OMP e-barr.Exclusive OpenMP Wait TimeExcl. OMP WaitInclusive OpenMP Wait TimeIncl. OMP WaitAttributed OpenMP Wait TimeAttr. OMP WaitExclusive OpenMP Serial TimeExcl. OMP serlInclusive OpenMP Serial TimeIncl. OMP serlAttributed OpenMP Serial TimeAttr. OMP serlExcl. OMP rducIncl. OMP rducAttr. OMP rducExcl. OMP lkwtIncl. OMP lkwtAttr. OMP lkwtExcl. OMP ctwtIncl. OMP ctwtAttr. OMP ctwtExcl. OMP odwtIncl. OMP odwtAttr. OMP odwtExcl. OMP ser.Incl. OMP ser.Attr. OMP ser.Excl. OMP snglIncl. OMP snglAttr. OMP snglExcl. OMP orddIncl. OMP orddAttr. OMP orddExclusive Race AccessesExcl. Race AccessesInclusive Race AccessesIncl. Race AccessesAttributed Race AccessesAttr. Race AccessesExclusive DeadlocksExcl. DeadlocksInclusive DeadlocksIncl. DeadlocksAttributed DeadlocksAttr. Deadlocks%s%s%s%s-%seiad.!.+%!e.any:named.any:namea.any:nameei.any:nameSource file `%s' not readableObject file `%s' not readableAnnotation computation error! //%%%ds: %%-%ds%%%ds: %%s[0x%08X,%6lld] %4d %6d %s LeftoverCompile flags: %sTotal* %.*s%s%*c <===----<<<%-50s %sstatsqwarningq||HWCTAG==&& ((HWCINT & )==0)Processing Experiment: %sNo nodes associated with %s 0x%08x -- %s %s 0x%016llX -- %s %s %s%-*s%*s%s %*s: %*s ( 0. %%)%*.3f (%5.1f%%)md = %lld, mw = %lld Error: report is too long. print Memory Leaks Statistics Write Statistics Read Statistics Other I/O Statistics I/O Error Statistics Instances = %d Bytes Allocated = %lld Bytes Leaked = %lld Write Time=%.6f (secs.) Write Bytes=%lld Write Count=%d Read Time=%.6f (secs.) Read Bytes=%lld Read Count=%d Other I/O Time=%.6f (secs.) Other I/O Count=%d I/O Error Time=%.6f (secs.) I/O Error Count=%d Start Label%*s: %s End LabelStart Time (sec.)End Time (sec.)Duration (sec.)Total Thread Time (sec.)%*s: %*.3fAverage number of ThreadsProcess Times (sec.)%*s: %.3lf%*s: %*s Experiment GroupExperimentExp.#%dError messageNo errors Experiment headerEmpty header Warning messageNo warnings Notes.class> Load Object Coverage: Experiment: %s Functions sorted by metric: PCs sorted by metric: Lines sorted by metric: Objects sorted by metric: ## %*s. %*c%*c[%*s] %*c[%*d] |+-Functions Call Tree. Metric: No CallersStack Fragment %s%s No CalleesSource FileObject FileLoad ObjectMangled NameAliasesScopeMember ofOffset (bytes)Size (bytes)Elements %*s: ( 0. %%) (%5.1f%%) (Global) (Synthetic) Get_Hist_data call failed %d No leak information No allocation information Individual samples %*s Sample Number%*s: %d %s

%s

∇  (%s) "%s"%c"V %s"%c" %s"%c"V "%c"V (%s)"%c" "%c" (%s)"%cXML parse error %d '%s' = '%s' expertnosonamemangledsrcLines != NULLError: %s html"&<>%s%3.2f"0."%c"%4.3lf"%c"%d"%c"%lld"%c"%llu"%c"%u:0x%08x"%c"%4.3f"%c"%3.2f"%c?>Invalid commentary classes: =# %s:%s%s:%s:nameOFFDELTARATIOsetting_commentqError: empty file name./.gprofng.rcGPROFNG_SYSCONFDIR%s/gprofng.rc/etc%s/.gprofng.rclwprootdepthbasicparallelquerymemopscodegenasrcnosrcnohexcfASSERT_SKIP %3d: %5d '%s' SymLstLocalLstN_UNDFN_ABSN_TEXTN_DATAN_BSSN_COMMN_FNN_EXTN_GSYMN_FNAMEN_FUNN_OUTLN_STSYMN_TSTSYMN_LCSYMN_TLCSYMN_MAINN_ROSYMN_FLSYMN_TFLSYMN_PCN_CMDLINEN_OBJN_OPTN_RSYMN_SLINEN_XLINEN_ILDPADN_SSYMN_ENDMN_SON_MODN_EMODN_READ_MODN_ALIASN_LSYMN_BINCLN_SOLN_PSYMN_EINCLN_ENTRYN_SINCLN_LBRACN_EXCLN_USINGN_ISYMN_ESYMN_PATCHN_CONSTRUCTN_DESTRUCTN_CODETAGN_FUN_CHILDN_RBRACN_BCOMMN_TCOMMN_ECOMMN_XCOMMN_ECOMLN_WITHN_LENGN_CPROFN_BROWSN_SO_ANSI_CN_SO_FORTRANN_SO_FORTRAN90N_SO_C99truefalse%u%ld%luPROFDATA_TYPE_SAMPLEPROFDATA_TYPE_GCEVENTPROFDATA_TYPE_HEAPSZPROFDATA_TYPE_CLOCKPROFDATA_TYPE_HWCPROFDATA_TYPE_SYNCHPROFDATA_TYPE_HEAPPROFDATA_TYPE_OMPPROFDATA_TYPE_OMP2PROFDATA_TYPE_OMP3PROFDATA_TYPE_OMP4PROFDATA_TYPE_OMP5PROFDATA_TYPE_IOTRACEHeap SizeClock ProfilingHW Counter ProfilingSynchronization TracingHeap TracingOpenMP ProfilingIO Tracingv1 == v2.loops.loopview%*s%*s%s%*s%*s%*s%s%sLoop below is parallelized: loop contains procedure callloop contains multiple exitsSource:n_type=%dgcc2_compiled.__KAI_KPTS___KAI_KCC___KAI_Kcc___KAI_KFMAIN.compcom.compcom1Minor Page FaultsMajor Page FaultsProcess swapsInput blocksOutput blocksMessages sentMessages receivedSignals handledVoluntary context switchesInvoluntary context switchesSystem callsCharacters of I/OQLParser.tab.hh!yytypeid_*yytypeid_ == typeid (T)__n < this->size()Syntax error after =Unclosed "SOMEORDEREDTRUEFALSEHAS_PROPJGROUPJPARENTDNAMEFILEIOVFDSyntax errorvector::_M_realloc_append!this->empty()/proc/cpuinfocpu MHzcpu familyvendor_idmvendoridmodel nameCPU implementerCPU architectureUnknown processorUnknown cpu modelbool DataView::checkUpdate()testName not foundShifting/usr/share/localegprofng+0. %+.3lf%+lld%u:0x%08x%.3f%huv1->tag == v2->tag>99.999<-99.999><)(Invalid process pid `%s' unlimitedUnrecognized size limit `%s' user interrupt Can't fstat group file %s Can't access group file %s Can't update group file %s Can't open group file %s: %s Unable to lock group file %s strlen (str) == newstrlen - 1usedldobjectsusedsrcInvalid sample signal %d %s.%d.er%s%d.er%ds-0s%ds-%ds0s-%dson %son threshold: calibrateon threshold: allon threshold: %don static(fork)Can't set SIGPROF: %s Can't reset SIGPROF: %s highJAVA_COMPILED_METHODSUnresolvablelibjvm.solibmtsk.soCollection parameters: experiment enabled target = %s user_expt_name = %s expt_name = %s dir_name = %s expt_group = %s debug_mode enabled Native-APIs Native- and Java-APIs %u. %s heap tracing enabled I/O tracing enabled count data enabled java profiling disabled sample signal %s (%d) sample signal %d periodic sampling, %d secs. no periodic sampling experiment archiving: -a %s data descriptor: "%s" ,rcollect-p%du-h-H-i-s,%d-F-a-j-y%d%s-l-S-L-g-d-oSP_COLLECTOR_FROM_GUI,P:%s;g:%d;d:%d%s;p:%d;s:%d,%d;H:%s;i:;h:%st:%d:%d;t:%d;S:%d;L:%d;j:%d;F:%d;a:%s;Can't set directory `%s': %s || ( str_expr=' atime=%09llu all_times=' comment='m4m5m6m7genericANALYZER_DATASPACE_COUNTSample signal %d%s/kallmodsyms%llx %llx %c %s [%sctf__per_cpu_start__per_cpu_end__crc___ksymtab___kcrctab___kstrtab___param___syscall_meta____p_syscall_meta____event_ftrace_event_types__args____tracepoint___tpstrtab___tpstrtab____initcall___setup___pci_fixup___dta___dtrace_probe_.clone.%s`%s(EXPGRID==%d && %s)(%s || %s)%s; %shwc2_profUnknown controlpause_resume_sigsample_sigjavaprofInternal errorclkprofprof_idledescendantarch_exptime_limitexp_limit%s/%dError: errno=%d (%s) /bin/ls -dl drwxrwxr-x-rwxrwxr-xExperiment Load CancelledK_c_stalls%s%s (plus %d more)Compare Group %d : Compare Group : Base Group : Target : '%s' Host : %s (%s, %s)Experiment :FK_SECTIONGlobal Definitions%s [EXPGRID==%d](%d) -> %s [%s, PID %d]FK_EXPLISTExperiments(%d) -> %s../@/bin/ls -aF/bin/ps -ef/bin/mkdir -p %s 2>&1/bin/rmdir %s 2>&1/bin/rm %s 2>&1 Error: Cannot open file %s ERRORSWARNINGSLEAF IN SOME IN DOBJYXXX_TOTAL_TIME_PLUS_THREADS%0.3f %sINSTRUCTIONSOURCELINELinesFunction + offset* +offset .element %*c. %*d. MET_NORMALMET_CALLMET_CALL_AGRMET_DATAMET_INDXMET_IOMET_HEAPCALLERSCALLEESSELFIOACTFILEIOACTVFDIOCALLSTACKHEAPCALLSTACKPrint not availableSource File: %sUnknownProcess%lld:0x%08llX(Unknown)Multiple Selection%s%s%s (%lld %s)Memory ObjectIndex Object(Synthetic)(Global)%s(%s)Offset Size Name %6lld %5lld %s Data ObjectOffsetListI/O ActivityHeap ActivityFAIRMAXMINAVGSIGUSR1SIGUSR2SIGPROFEVT_COUNTtmp_end_bin < numDeltastmp_start_bin < numDeltasprop_ts == -1kill(%d, %d) failed: %s Write StatisticsRead StatisticsOther I/O StatisticsI/O Error Statistics0KB - 1KB1KB - 8KB8KB - 32KB32KB - 128KB128KB - 256KB256KB - 512KB512KB - 1000KB1000KB - 10MB10MB - 100MB100MB - 1GB1GB - 10GB10GB - 100GB100GB - 1TB1TB - 10TBLongest write%.6f (secs.)Smallest write bytesLargest write bytesTotal timeTotal callsTotal bytesLongest readSmallest read bytesLargest read bytesMemory Allocations StatisticsMemory Leaks StatisticsHeap size bytesProcess IdTime of peak%.3f (secs.)Smallest allocation bytesLargest allocation bytesTotal allocationsSmallest leaked bytesLargest leaked bytesTotal leakedGenuineIntelAuthenticAMDpicnum.constprop.___gnu_compiledUnknown AMD processorAMD Opteron & Athlon64AMD Family 10hAMD Family 19h (Zen3)AMD Family 19h (Zen4)CPU-cyclesref-cycles%-*s %-*s%c%*s%*s %sSIGHUP.text$CODE$%s: file has no symbols rbgmoncounter `%s' is not valid umaskattribute `%s' is invalid Processor not supported ~UNKNOWN~%s=0x%llxer_kernellohi%s EventsUndefined Eventsload load-store memoryspace count not-program-related HW counter not available (`%s'; %s%s) (%s%s)%s,%s%sSignal %dinsts,,cycles,,l3minsts,,cyclesInvalid HW counter name: %s auto[/][[~=]...] -h {auto|lo|on|hi} -h counter name, Counter name ~= `%s' Default set of HW counters: -h %s unitstype raw name Raw HW counters: Instr_all internal use of SPR ring %s Instr_SPR_ring_ops %-19s %s Branches that are takenblock load/storeInstr_block_ld_statomic instructionsInstr_atomicInstr_SW_prefetchInstr_SW_counthit own L1 data cache %-22s %s hit own L2hit own L3DC_miss_L3_hithit neighbor L2 (same scc)DC_miss_nbr_L2_hitDC_miss_nbr_scc_hitDC_miss_nbr_scc_missall - DC_hitDC_missall - DC_hit - DC_miss_L2_hitDC_miss_L2_missDC_miss_L3_misshit cache on different socketDC_miss_remote_scc_hitDC_miss_local_mem_hitDC_miss_remote_mem_hit DC_miss_commit %s %s %s Br_tgt_mispredFlush_L3_missbranch mispredictionFlush_br_mispredFlush_arch_exceptionFlush_otherBlock_ld_stAtomicsSw_count_intrDC_miss_L3_dirty_copybackhit neighbor L3 (same socket)DC_miss_nbr_L3_hitDC_miss_remote_L3_hitBr_trg_mispred RAW_hit e.user:nameusr_timesys_timecycles~system=1~user=0branch-instructionsBranch-instructionsbranch-missesBranch-missesbus-cyclesBus Cyclescache-missesCache-missescache-referencesCache-referencesInstructions ExecutedTotal Cyclesstalled-cycles-backendStalled Cycles during issue.stalled-cycles-frontendalignment-faultsAlignment Faultscontext-switchesContext Switchescpu-clockCPU Clockcpu-migrationsCPU Migrationsemulation-faultsEmulation Faultsmajor-faultsminor-faultspage-faultstask-clockClock Count SpecificL1-dcache-load-missesL1 D-cache Load MissesL1-dcache-loadsL1 D-cache LoadsL1-dcache-store-missesL1 D-cache Store MissesL1-dcache-storesL1 D-cache Store StoresL1-icache-load-missesL1 Instructions Load MissesL1 Instructions LoadsdTLB-load-missesD-TLB Load MissesdTLB-loadsD-TLB LoadsiTLB-load-missesiTLB-loadsThe Instruction TLB Loadsbp_de_redirectbp_dyn_ind_predbp_l2_btb_correctex_ret_brnex_ret_brn_farex_ret_brn_ind_mispex_ret_brn_mispex_ret_brn_tknex_ret_brn_tkn_mispex_ret_condex_ret_ind_brch_instrex_ret_near_retex_ret_near_ret_mispredex_ret_uncond_brnch_instric_cache_fill_l2ic_cache_fill_sysInstruction cache hitsInstruction cache missesl2_cache_req_stat.alll2_cache_req_stat.ls_rd_blk_cl2_cache_req_stat.ls_rd_blk_xl2_pf_hit_l2.alll2_pf_hit_l2.l1_regionl2_pf_hit_l2.l1_streaml2_pf_hit_l2.l1_stridel2_pf_hit_l2.l2_burstl2_pf_hit_l2.l2_next_linel2_pf_hit_l2.l2_streaml2_pf_hit_l2.l2_stridel2_pf_hit_l2.l2_up_downl2_pf_miss_l2_hit_l3.alll2_pf_miss_l2_hit_l3.l2_burstl2_pf_miss_l2_l3.alll2_pf_miss_l2_l3.l1_regionl2_pf_miss_l2_l3.l1_streaml2_pf_miss_l2_l3.l1_stridel2_pf_miss_l2_l3.l2_burstl2_pf_miss_l2_l3.l2_next_linel2_pf_miss_l2_l3.l2_streaml2_pf_miss_l2_l3.l2_stridel2_pf_miss_l2_l3.l2_up_downl2_request_g1.alll2_request_g1.all_dcl2_request_g1.all_no_prefetchl2_request_g1.change_to_xl2_request_g1.group2l2_request_g1.l2_hw_pfl2_request_g1.ls_rd_blk_c_sl2_request_g1.prefetch_l2_cmdl2_request_g1.rd_blk_ll2_request_g1.rd_blk_xls_alloc_mab_countls_any_fills_from_sys.allls_any_fills_from_sys.far_allls_dmnd_fills_from_sys.allls_hw_pf_dc_fills.allls_hw_pf_dc_fills.dram_io_farls_hw_pf_dc_fills.far_cachels_hw_pf_dc_fills.local_ccxls_hw_pf_dc_fills.local_l2ls_hw_pf_dc_fills.near_cachels_inef_sw_pref.all(null)ls_inef_sw_pref.mab_mch_cntls_mab_alloc.all_allocationsls_pref_instr_disp.allls_pref_instr_disp.prefetchls_pref_instr_disp.prefetch_wls_sw_pf_dc_fills.allls_sw_pf_dc_fills.dram_io_farls_sw_pf_dc_fills.far_cachels_sw_pf_dc_fills.local_ccxls_sw_pf_dc_fills.local_l2ls_sw_pf_dc_fills.near_cacheOp cache hitsOp cache missesex_div_busyex_div_countDivide ops executedex_no_retire.allex_no_retire.emptyex_no_retire.not_completeex_no_retire.otherex_ret_fused_instrRetired fused instructionsex_ret_instrRetired instructionsex_ret_opsRetired macro-opsex_ret_ucode_instrex_ret_ucode_opsRetired microcode opsOps tagged by IBSls_int_takenInterrupts takenls_locks.bus_lockls_not_halted_cycCore cycles not in haltls_ret_cl_flushRetired CLFLUSH instructionsls_ret_cpuidRetired CPUID instructionsls_smi_rxSMIs receivedfp_disp_faults.allfp_disp_faults.sse_avx_allfp_disp_faults.x87_fill_faultfp_disp_faults.xmm_fill_faultfp_disp_faults.ymm_fill_faultfp_ops_retired_by_type.allfp_ops_retired_by_width.allfp_pack_ops_retired.allfp_pack_ops_retired.fp128_addfp_pack_ops_retired.fp128_allfp_pack_ops_retired.fp128_cmpfp_pack_ops_retired.fp128_cvtfp_pack_ops_retired.fp128_divfp_pack_ops_retired.fp128_macfp_pack_ops_retired.fp128_mulfp_pack_ops_retired.fp128_subfp_pack_ops_retired.fp256_addfp_pack_ops_retired.fp256_allfp_pack_ops_retired.fp256_cmpfp_pack_ops_retired.fp256_cvtfp_pack_ops_retired.fp256_divfp_pack_ops_retired.fp256_macfp_pack_ops_retired.fp256_mulfp_pack_ops_retired.fp256_subfp_ret_sse_avx_ops.allfp_ret_sse_avx_ops.div_flopsfp_ret_sse_avx_ops.mac_flopsfp_ret_sse_avx_ops.mult_flopsfp_ret_x87_fp_ops.add_sub_opsfp_ret_x87_fp_ops.allfp_ret_x87_fp_ops.mul_opsfp_retired_ser_ops.allpacked_int_op_type.allpacked_int_op_type.int128_addpacked_int_op_type.int128_aespacked_int_op_type.int128_allpacked_int_op_type.int128_clmpacked_int_op_type.int128_cmppacked_int_op_type.int128_macpacked_int_op_type.int128_movpacked_int_op_type.int128_mulpacked_int_op_type.int128_shapacked_int_op_type.int128_subpacked_int_op_type.int256_addpacked_int_op_type.int256_allpacked_int_op_type.int256_cmppacked_int_op_type.int256_macpacked_int_op_type.int256_movpacked_int_op_type.int256_mulpacked_int_op_type.int256_subsse_avx_ops_retired.allsse_avx_ops_retired.mmx_addRetired MMX integer addsse_avx_ops_retired.mmx_allsse_avx_ops_retired.mmx_cmpsse_avx_ops_retired.mmx_macsse_avx_ops_retired.mmx_movRetired MMX integer MOV opssse_avx_ops_retired.mmx_mulsse_avx_ops_retired.mmx_othersse_avx_ops_retired.mmx_packRetired MMX integer pack opssse_avx_ops_retired.mmx_shiftRetired MMX integer shift opssse_avx_ops_retired.mmx_subbp_l1_tlb_fetch_hit.allbp_l1_tlb_fetch_hit.if1gbp_l1_tlb_fetch_hit.if2mbp_l1_tlb_fetch_hit.if4kbp_l1_tlb_miss_l2_tlb_hitls_bad_status2.stli_otherls_dispatch.ld_dispatchls_dispatch.ld_st_dispatchls_dispatch.store_dispatchls_l1_d_tlb_miss.allls_l1_d_tlb_miss.all_l2_missls_misal_loads.ma4kls_misal_loads.ma64ls_stlfls_tlb_flush.allAll TLB Flushesde_op_queue_emptyde_src_op_disp.allde_src_op_disp.decoderde_src_op_disp.loop_bufferde_src_op_disp.op_cacheresyncs_or_nc_redirectsall_data_cache_accessesAll data cache accessesDecode RedirectsDynamic Indirect Predictionsbp_l1_btb_correctbp_l1_tlb_fetch_hitbp_tlb_relbp_l1_tlb_miss_l2_tlb_missbp_snp_re_syncic_fetch_stall.ic_stall_anyic_fw32ic_fw32_missl2_fill_pending.l2_fill_busyl2_pf_hit_l2l2_pf_miss_l2_hit_l3l2_pf_miss_l2_l3l2_request_g2.group1l2_request_g2.ic_rd_sizedl2_request_g2.ic_rd_sized_ncl2_request_g2.ls_rd_sizedl2_request_g2.ls_rd_sized_ncl2_request_g2.smc_invall2_wcb_req.cl_zerol2_wcb_req.wcb_closel2_wcb_req.wcb_writel2_wcb_req.zero_byte_storeDiv Cycles Busy countDiv Op CountRetired Branch InstructionsRetired Far Control Transfersex_ret_brn_resyncRetired Branch ResyncsRetired Instructionsex_ret_mmx_fp_instr.mmx_instrMMX instructionsex_ret_mmx_fp_instr.sse_instrex_ret_mmx_fp_instr.x87_instrx87 instructionsRetired Near Returnsfpu_pipe_assignment.totalTotal number of fp uOpsfpu_pipe_assignment.total0fpu_pipe_assignment.total1fpu_pipe_assignment.total2fpu_pipe_assignment.total3Count of Allocated Mabsls_any_fills_from_sys.lcl_l2ls_dc_accessesls_dmnd_fills_from_sys.lcl_l2ls_hw_pf_dc_fills.int_cachels_hw_pf_dc_fills.lcl_l2ls_locks.non_spec_lockls_locks.spec_lock_hi_specls_locks.spec_lock_lo_specls_mab_alloc.dc_prefetcherls_mab_alloc.loadsls_mab_alloc.storesCycles not in Haltls_pref_instr_displs_rdtscNumber of STLF hitsls_sw_pf_dc_fills.int_cachels_sw_pf_dc_fills.lcl_l2ls_tablewalker.dc_type0ls_tablewalker.dc_type1ls_tablewalker.dsidels_tablewalker.ic_type0ls_tablewalker.ic_type1ls_tablewalker.isidels_tlb_flush.all_tlb_flushesde_dis_uop_queue_empty_di0All L1 Data Cache Accessesall_tlbs_flushedAll TLBs Flushedl1_data_cache_fills_allL1 Data Cache Fills: Alll1_dtlb_missesL1 DTLB Missesl2_cache_hits_from_dc_missesl2_cache_hits_from_ic_missesl2_cache_hits_from_l2_hwpfl2_cache_misses_from_ic_missl2_dtlb_missesl2_itlb_missesmacro_ops_retiredMacro-ops Retiredsse_avx_stallsMixed SSE/AVX StallskcyclesKCPU CycleskucyclesKUCPU CycleskthrKTHR CyclesCU_cpu_clk_unhaltedEX_retired_instr_w_excp_intrIC_fetchL1 I-cache RefsIC_missL1 I-cache Missesl2imIC_refill_from_systemL2 I-cache MissesDC_accessL1 D-cache RefsDC_miss~umask=0x3L1 D-cache Missesl2dmDC_refill_from_systemL2 D-cache MissesDC_unified_tlb_miss~umask=0x7L2 DTLB MissesFP_scheduler_emptyFP_bottom_execute_uops_cyclesLS_ldq_stq_fullLS_locked_operationCU_mab_wait_cyclesIC_instr_fetch_stallEX_intr_masked_cyclesDE_nothing_to_dispatchDE_dispatch_stallsDE_dispatch_stall_ldq_fullEX_dispatch_stall_stq_fullcycles0cycles1insts0insts1BU_cpu_clk_unhaltedl2itlbhIC_itlb_L1_miss_L2_hitL2 ITLB Hitsl2itlbmIC_itlb_L1_miss_L2_missL2 ITLB Missesl2irBU_internal_L2_req~umask=0x1L2 I-cache Refsl2dtlbhDC_dtlb_L1_miss_L2_hitL2 DTLB HitsDC_dtlb_L1_miss_L2_missl2drBU_internal_L2_req~umask=0x2L2 D-cache RefsfpaddFP AddsfpmulFP MulsfpustallFR_dispatch_stall_fpu_fullFPU Stall CyclesmemstallFR_dispatch_stall_ls_fullMemory Unit Stall CyclesFP_cycles_no_fpu_ops_retiredFP_serialize_ops_cyclesFR_dispatch_stallsFR_intr_masked_cyclesFR_nothing_to_dispatchLS_buffer_2_fullNB_mem_ctrlr_turnaroundcpu_clk_unhalted.corecpu_clk_unhalted.threadinstr_retired.anypage_walks.cyclesl2_adsl2_dbus_busyl2_no_reqcpu_clk_unhalted.core_pcpu_clk_unhalted.buscpu_clk_unhalted.no_otherbus_drdy_clocksbus_lock_clocksbus_data_rcvbus_hit_drvbus_hitm_drvbusq_emptysnoop_stall_drvbus_io_waitunhalted-core-cyclesinst_retired.any_pPERF_COUNT_HW_CPU_CYCLESPERF_COUNT_HW_INSTRUCTIONSllc-missesLast-Level Cache MissesPERF_COUNT_HW_CACHE_MISSES.LLbranch-misses-retiredBranch MispredictPERF_COUNT_HW_BRANCH_MISSESbranch-instruction-retiredunhalted-reference-cyclesPERF_COUNT_HW_BUS_CYCLESl1d.replacementl1d_pend_miss.fb_fulll1d_pend_miss.fb_full_periodsl1d_pend_miss.l2_stalll1d_pend_miss.pendingl1d_pend_miss.pending_cyclesl2_lines_in.allL2 cache lines filling L2l2_lines_out.non_silentl2_lines_out.silentl2_rqsts.all_code_rdL2 code requestsl2_rqsts.all_demand_data_rdDemand Data Read requestsl2_rqsts.all_demand_missl2_rqsts.all_rfoRFO requests to L2 cachel2_rqsts.code_rd_hitl2_rqsts.code_rd_missl2_rqsts.demand_data_rd_hitl2_rqsts.demand_data_rd_missl2_rqsts.rfo_hitl2_rqsts.rfo_missl2_rqsts.swpf_hitl2_rqsts.swpf_missl2_trans.l2_wblongest_lat_cache.misslongest_lat_cache.referencemem_inst_retired.all_loadsmem_inst_retired.all_storesmem_inst_retired.anymem_inst_retired.lock_loadsmem_inst_retired.split_loadsmem_inst_retired.split_storesmem_load_misc_retired.ucmem_load_retired.fb_hitmem_load_retired.l1_hitmem_load_retired.l1_missmem_load_retired.l2_hitmem_load_retired.l2_missmem_load_retired.l3_hitmem_load_retired.l3_missmem_load_retired.local_pmmocr.demand_code_rd.l3_hitocr.demand_data_rd.l3_hitocr.demand_rfo.l3_hitocr.demand_rfo.snc_cache.hitmocr.hwpf_l1d_and_swpf.l3_hitocr.hwpf_l3.l3_hitocr.prefetches.l3_hitocr.reads_to_core.l3_hitocr.streaming_wr.l3_hitoffcore_requests.all_data_rdoffcore_requests.all_requestsoffcore_requests.demand_rfosq_misc.bus_locksq_misc.sq_fullsw_prefetch_access.ntasw_prefetch_access.prefetchwsw_prefetch_access.t0sw_prefetch_access.t1_t2assists.fpfp_arith_inst_retired.4_flopsfp_arith_inst_retired.8_flopsfp_arith_inst_retired.scalarfp_arith_inst_retired.vectorbaclears.anydecode.lcpdsb2mite_switches.countfrontend_retired.any_dsb_missfrontend_retired.dsb_missfrontend_retired.itlb_missfrontend_retired.l1i_missfrontend_retired.l2_missfrontend_retired.latency_ge_1frontend_retired.latency_ge_2frontend_retired.latency_ge_4frontend_retired.latency_ge_8frontend_retired.stlb_missicache_16b.ifdata_stallicache_64b.iftag_hiticache_64b.iftag_missicache_64b.iftag_stallicache_data.stallsicache_tag.stallsidq.dsb_cycles_anyidq.dsb_cycles_okidq.dsb_uopsidq.mite_cycles_anyidq.mite_cycles_okidq.mite_uopsidq.ms_switchesidq.ms_uopsidq_uops_not_delivered.corecycle_activity.stalls_l3_missocr.demand_code_rd.l3_missocr.demand_data_rd.l3_missocr.demand_rfo.l3_missocr.demand_rfo.l3_miss_localocr.hwpf_l1d_and_swpf.l3_missocr.hwpf_l3.l3_missocr.hwpf_l3.l3_miss_localocr.itom.l3_miss_localocr.other.l3_missocr.other.l3_miss_localocr.prefetches.l3_miss_localocr.reads_to_core.l3_missocr.streaming_wr.l3_missrtm_retired.abortedrtm_retired.aborted_eventsrtm_retired.aborted_memrtm_retired.aborted_memtypertm_retired.commitrtm_retired.starttx_exec.misc2tx_exec.misc3tx_mem.abort_capacity_readtx_mem.abort_capacity_writetx_mem.abort_conflictcore_power.lvl0_turbo_licensecore_power.lvl1_turbo_licensecore_power.lvl2_turbo_licensecore_snoop_response.i_fwd_fecore_snoop_response.i_fwd_mcore_snoop_response.i_hit_fsecore_snoop_response.missLine not found snoop replycore_snoop_response.s_fwd_fecore_snoop_response.s_fwd_mcore_snoop_response.s_hit_fseocr.demand_code_rd.dramocr.demand_code_rd.local_dramocr.demand_code_rd.snc_dramocr.demand_data_rd.dramocr.demand_data_rd.local_dramocr.demand_data_rd.local_pmmocr.demand_data_rd.pmmocr.demand_data_rd.remote_pmmocr.demand_data_rd.snc_dramocr.demand_data_rd.snc_pmmocr.demand_rfo.any_responseocr.demand_rfo.dramocr.demand_rfo.local_dramocr.demand_rfo.local_pmmocr.demand_rfo.pmmocr.demand_rfo.remote_pmmocr.demand_rfo.snc_dramocr.demand_rfo.snc_pmmocr.hwpf_l1d_and_swpf.dramocr.hwpf_l2.any_responseocr.hwpf_l3.any_responseocr.hwpf_l3.remoteocr.itom.remoteocr.other.any_responseocr.reads_to_core.dramocr.reads_to_core.local_dramocr.reads_to_core.local_pmmocr.reads_to_core.remoteocr.reads_to_core.remote_dramocr.reads_to_core.remote_pmmocr.reads_to_core.snc_dramocr.reads_to_core.snc_pmmocr.streaming_wr.any_responseocr.write_estimate.memoryarith.divider_activebr_inst_retired.all_branchesbr_inst_retired.condbr_inst_retired.cond_ntakenbr_inst_retired.cond_takenbr_inst_retired.far_branchbr_inst_retired.indirectbr_inst_retired.near_callbr_inst_retired.near_returnbr_inst_retired.near_takenbr_misp_retired.all_branchesbr_misp_retired.condbr_misp_retired.cond_ntakenbr_misp_retired.cond_takenbr_misp_retired.indirectbr_misp_retired.indirect_callbr_misp_retired.near_takenbr_misp_retired.retcpu_clk_unhalted.distributedcpu_clk_unhalted.ref_tsccpu_clk_unhalted.ref_xclkcpu_clk_unhalted.thread_pcycle_activity.cycles_l2_misscycle_activity.cycles_mem_anycycle_activity.stalls_l2_misscycle_activity.stalls_mem_anycycle_activity.stalls_totalTotal execution stallsexe_activity.1_ports_utilexe_activity.2_ports_utilexe_activity.3_ports_utilexe_activity.4_ports_utilexe_activity.bound_on_storesild_stall.lcpinst_decoded.decodersinst_retired.nopinst_retired.prec_distint_misc.all_recovery_cyclesint_misc.clear_resteer_cyclesint_misc.clears_countClears speculative countint_misc.recovery_cyclesint_misc.uop_droppingld_blocks.no_srld_blocks.store_forwardload_hit_prefetch.swpflsd.cycles_activelsd.cycles_oklsd.uopsmachine_clears.countmachine_clears.smcmisc_retired.lbr_insertsmisc_retired.pause_instresource_stalls.sbresource_stalls.scoreboardrs_events.empty_cyclesrs_events.empty_endtopdown.backend_bound_slotstopdown.slotstopdown.slots_puops_decoded.dec0uops_dispatched.port_0uops_dispatched.port_1uops_dispatched.port_2_3uops_dispatched.port_4_9uops_dispatched.port_5uops_dispatched.port_6uops_dispatched.port_7_8uops_executed.cycles_ge_1uops_executed.cycles_ge_2uops_executed.cycles_ge_3uops_executed.cycles_ge_4uops_executed.stall_cyclesuops_executed.threaduops_executed.x87uops_issued.anyUops that RAT issues to RSuops_issued.stall_cyclesuops_retired.slotsRetirement slots useduops_retired.stall_cyclesuops_retired.total_cyclesdtlb_load_misses.stlb_hitdtlb_load_misses.walk_activedtlb_load_misses.walk_pendingdtlb_store_misses.stlb_hitdtlb_store_misses.walk_activeitlb_misses.stlb_hititlb_misses.walk_activeitlb_misses.walk_completeditlb_misses.walk_completed_4kitlb_misses.walk_pendingtlb_flush.dtlb_threadtlb_flush.stlb_anySTLB flush attemptscpu_clk_unhalted.ref_pl2m_latencyL2 Cache Miss Est. LatencyL1 D-cache Hitsl2hL2 Cache Hitsl2mL2 Cache Missesl2m_stallL2 Cache Miss Stalll3hL3 Cache HitsL3 Cache Missesl3m_stallL3 Cache Miss Stalldtlbm_stallDTLB Miss Est StallFP Scalar uOpsfp_vectorFP Vector uOpsint_misc.recovery_cycles_anycpu_clk_unhalted.ring0_transcpu_clk_unhalted.thread_p_anyept.walk_pendingidq.mite_cyclesidq.dsb_cyclesidq.ms_dsb_cyclesidq.all_dsb_cycles_4_uopsidq.all_dsb_cycles_any_uopsidq.all_mite_cycles_4_uopsidq.all_mite_cycles_any_uopsidq.ms_cyclesuops_dispatched_port.port_0uops_dispatched_port.port_1uops_dispatched_port.port_2uops_dispatched_port.port_3uops_dispatched_port.port_4uops_dispatched_port.port_5uops_dispatched_port.port_6uops_dispatched_port.port_7resource_stalls.anycycle_activity.cycles_l3_misslsd.cycles_4_uopsinst_retired.total_cycles_psfp_assist.anymem_load_uops_retired.l1_hitmem_load_uops_retired.l1_missmem_load_uops_retired.l2_hitmem_load_uops_retired.l2_missmem_load_uops_retired.l3_hitmem_load_uops_retired.l3_missuops_issued.core_stall_cyclesarith.fpu_div_activeept.walk_cyclescpl_cycles.ring0cpl_cycles.ring0_transcpl_cycles.ring123idq.emptyitlb_misses.walk_durationuops_executed_port.port_0uops_executed_port.port_1uops_executed_port.port_2uops_executed_port.port_3uops_executed_port.port_4uops_executed_port.port_5uops_executed_port.port_6uops_executed_port.port_7resource_stalls.rsresource_stalls.robmachine_clears.cycles0xd1~umask=0x080xd1~umask=0x10L3 Cache Hit w/o Snoop0xd1~umask=0x20idq.ms_mite_uops_cyclesidq.ms_mite_cyclesicache.ifetch_stallild_stall.iq_fullmem_load_uops_retired.llc_hitint_misc.rat_stall_cyclesresource_stalls2.all_fl_emptyresource_stalls2.bob_fullresource_stalls2.ooo_rsrccpl_cycles.ring0_transitionidq.all_dsb_cyclesidq.all_mite_cyclesidq.mite_all_cyclesresource_stalls.lbresource_stalls.lb_sbresource_stalls.mem_rsresource_stalls.fcswresource_stalls.mxcsrresource_stalls.otherresource_stalls.ooo_rsrcuops_dispatched.stall_cyclesuops_retired.active_cyclesmem_load_retired.l1d_hit0xCB~umask=0x1eL1 D-Cache Misseslfbdhmem_load_retired.hit_lfbLFB D-cache Hits0xCB~umask=0x1cl3h_stalll3hsnoopL3 Cache Hit w/Snoopl3hsnoop_stallmem_load_retired.llc_missaddr_alias_stallpartial_address_aliasuope_stallUOP Execute Stalls per Coreuopr_stallUOP Retired Stallsitlb_miss_retiredl1i_stalll1i.cycles_stalledL1 I-cache Stallsbr_retsBranch Instruction Retiresbr_mispbr_misp_exec.anyBranch Mispredictsmach_clearMachine Clear Assertedfp_mmxfp_mmx_trans.anyFP-MMX Transistionsarith.cycles_div_busyDivider Busy Cyclessb_drain.cyclesdtlb_load_misses.walk_cyclesmemory_disambiguation.resetinst_queue_write_cycleshw_int.cycles_maskeddtlb_misses.walk_cyclessfence_cyclescache_lock_cycles.l1dcache_lock_cycles.l1d_l2itlb_misses.walk_cyclesitlb_misses.pmh_busy_cyclesild_stall.mruild_stall.regenild_stall.anyresource_stalls.loadresource_stalls.rs_fullresource_stalls.storeresource_stalls.rob_fullresource_stalls.fpcwoffcore_requests_sq_fullrat_stalls.flagsrat_stalls.registersrat_stalls.rob_read_portrat_stalls.scoreboardrat_stalls.anyseg_rename_stallssq_full_stall_cyclesuops_stalleduOps Stalledmem_load_retired~umask=0x08L2 Line Missesmem_load_retired~umask=0x10l1mmem_load_retired~umask=0x02L1 Line Missesresource_stalls~umask=0x02Reservation Station Fullbr_miss_flushresource_stalls~umask=0x10Mispredicted Branch Flushesld_st_fullresource_stalls~umask=0x04Load/Store Buffers Fullresource_stalls~umask=0x01Reorder Buffer Fullslow_decodeild_stallSlow Instruction Decodebr_missbr_cnd_missp_execMispredicted Branchesret_missbr_call_missp_execMispredicted Return Callsidle_during_divDivider Unit Busyfp_assistsfp_assistFP Microcode Assistsbus_drdy_clocks~umask=0x60Busy Data Busstore_blockstore_block.drain_cyclesstore_block.orderstore_block.snoopdelayed_bypass.loadl2_dbus_busy_rdl1d_cache_lock.durationinst_queueinst_queue.fullcycles_l1i_mem_stalledrs_uops_dispatchedrs_uops_dispatched_portrs_uops_dispatched_port.0rs_uops_dispatched_port.1rs_uops_dispatched_port.2rs_uops_dispatched_port.3rs_uops_dispatched_port.4rs_uops_dispatched_port.5cycles_intcycles_int.maskedcycles_int.pending_and_maskedrat_stallsrat_stalls.partial_cyclesrat_stalls.fpswseg_rename_stalls.esseg_rename_stalls.dsseg_rename_stalls.fsseg_rename_stalls.gsseg_rename_stalls.anyresource_stallsresource_stalls.ld_stresource_stalls.br_miss_clearinstr_retired~emask=0x3L1 Cache MissesTC_deliver_modemachine_clearifu_ifetch_missI$ Missesdcrmdcu_m_lines_inD$ Read Missesdcwmdcu_m_lines_outD$ Write MissesFloating-point Opseciml2_ifetchE$ Instr. MissesedgecmaskHangupSIGINTInterruptSIGQUITQuitSIGILLIllegal instructionSIGTRAPTrace/breakpoint trapSIGIOTIOT trapSIGABRTAbortedSIGFPEArithmetic exceptionSIGKILLKilledSIGBUSBus errorSIGSEGVSegmentation faultSIGSYSBad system callSIGPIPEBroken pipeSIGALRMAlarm clockSIGTERMTerminatedUser defined signal 1User defined signal 2SIGCLDChild status changedSIGCHLDSIGPWRPower fail/restartSIGWINCHWindow size changedSIGURGUrgent I/O conditionSIGIOI/O possibleSIGPOLLPollable event occurredSIGSTOPStopped (signal)SIGTSTPStopped (user)SIGCONTContinuedSIGTTINStopped (tty input)SIGTTOUStopped (tty output)SIGVTALRMVirtual timer expiredProfiling timer expiredSIGXCPUCPU time limit exceededSIGXFSZFile size limit exceededPAPI_l1_dcmPAPI_l1_icmPAPI_l2_dcmPAPI_l2_icmPAPI_l3_dcmPAPI_l3_icmPAPI_l1_tcmPAPI_l2_tcmPAPI_l3_tcmPAPI_ca_snpPAPI_ca_shrPAPI_ca_clnPAPI_ca_invPAPI_ca_itvPAPI_l3_ldmPAPI_l3_stmPAPI_bru_idlPAPI_fxu_idlPAPI_fpu_idlPAPI_lsu_idlPAPI_tlb_dmPAPI_tlb_imPAPI_tlb_tlPAPI_tlb_tmPAPI_l1_ldmPAPI_l1_stmPAPI_l2_ldmPAPI_l2_stmPAPI_btac_mPAPI_prf_dmPAPI_l3_dchPAPI_tlb_sdPAPI_csr_falPAPI_csr_sucPAPI_csr_totPAPI_mem_scyPAPI_mem_rcyPAPI_mem_wcyPAPI_stl_icyPAPI_ful_icyPAPI_stl_ccyPAPI_ful_ccyPAPI_hw_intPAPI_br_ucnPAPI_br_cnPAPI_br_tknPAPI_br_ntkPAPI_br_mspPAPI_br_prcPAPI_fma_insPAPI_tot_iisPAPI_tot_insPAPI_int_insPAPI_fp_insPAPI_ld_insPAPI_sr_insPAPI_br_insPAPI_vec_insPAPI_res_stlPAPI_fp_stalPAPI_tot_cycPAPI_lst_insPAPI_syc_insPAPI_l1_dchPAPI_l2_dchPAPI_l1_dcaPAPI_l2_dcaPAPI_l3_dcaPAPI_l1_dcrPAPI_l2_dcrPAPI_l3_dcrPAPI_l1_dcwPAPI_l2_dcwPAPI_l3_dcwPAPI_l1_ichPAPI_l2_ichPAPI_l3_ichPAPI_l1_icaPAPI_l2_icaPAPI_l3_icaPAPI_l1_icrPAPI_l2_icrPAPI_l3_icrPAPI_l1_icwPAPI_l2_icwPAPI_l3_icwPAPI_l1_tchPAPI_l2_tchPAPI_l3_tchPAPI_l1_tcaPAPI_l2_tcaPAPI_l3_tcaPAPI_l1_tcrPAPI_l2_tcrPAPI_l3_tcrPAPI_l1_tcwPAPI_l2_tcwPAPI_l3_tcwPAPI_fml_insPAPI_fad_insPAPI_fdv_insPAPI_fsq_insPAPI_fnv_insPAPI_fp_opsinsts,,cycles,,l3m,,dtlbmcycles,,insts,,llminsts,,cycles,,l2dm,,l2dtlbmAMD Family 11hAMD Family 15h Model 01hAMD Family 15h Model 02hAMD Family 15h Model 03hPentium 4 with HyperThreadingPentium 4Pentium Pro, Pentium IIPentium with MMXPentiumCore MicroarchitectureIntel Arch PerfMonSPARC64 IIISPARC64 VSPARC64 VISPARC64 VI & VIISPARC64 XSPARC64 XIIUltraSPARC T1UltraSPARC T2UltraSPARC T2+SPARC T3SPARC T4SPARC M4SPARC T5SPARC M5SPARC T6SPARC M6SPARC T7SPARC 3e40SPARC M7SPARC 3e50UltraSPARC IV+UltraSPARC IVUltraSPARC IIIiUltraSPARC IIIi & IIIi+UltraSPARC III+UltraSPARC III+ & IVUltraSPARC IIIUltraSPARC I&IIllc-referenceuops_issued.slow_leal2_rqsts.pf_missl2_rqsts.missl2_rqsts.pf_hitl2_rqsts.all_pfl2_rqsts.referencesload_hit_pre.sw_pftx_mem.abort_capacitytx_exec.misc1tx_exec.misc4tx_exec.misc5idq.ms_mite_uopsitlb_misses.walk_completed_1gitlb.itlb_flushuops_executed.coreother_assists.anyuops_retired.retire_slotsbr_inst_retired.conditionalbr_inst_retired.not_takenbr_misp_retired.conditionalbr_misp_retired.near_callhle_retired.starthle_retired.commithle_retired.abortedhle_retired.aborted_memhle_retired.aborted_timerhle_retired.aborted_memtypehle_retired.aborted_eventsrtm_retired.aborted_timerhw_interrupts.receivedrob_misc_events.lbr_insertsl2_lines_out.useless_hwpfsq_misc.split_lockmisalign_mem_ref.loadsmisalign_mem_ref.storesdtlb_load_misses.stlb_hit_4kdtlb_load_misses.stlb_hit_2muops_issued.flags_mergeuops_issued.single_mull2_rqsts.l2_pf_missl2_rqsts.l2_pf_hitl2_demand_rqsts.wb_hitl1d_pend_miss.occurencesdtlb_store_misses.stlb_hit_4kdtlb_store_misses.stlb_hit_2mload_hit_pre.hw_pfidq.ms_dsb_uopsidq.ms_dsb_occuridq.mite_all_uopsicache.hiticache.missesicache.ifdata_stallitlb_misses.stlb_hit_4kitlb_misses.stlb_hit_2mbr_inst_exec.all_conditionalbr_inst_exec.all_direct_jmpbr_inst_exec.all_branchesbr_misp_exec.all_conditionalbr_misp_exec.all_branchespage_walker_loads.dtlb_l1page_walker_loads.itlb_l1page_walker_loads.dtlb_l2page_walker_loads.itlb_l2page_walker_loads.dtlb_l3page_walker_loads.itlb_l3page_walker_loads.dtlb_memorypage_walker_loads.itlb_memoryinst_retired.x87other_assists.avx_to_sseother_assists.sse_to_avxother_assists.any_wb_assistuops_retired.allmachine_clears.maskmovbr_inst_retired.near_call_r3fp_arith_inst_retired.doublefp_arith_inst_retired.singlefp_arith_inst_retired.packedhle_retired.aborted_misc1hle_retired.aborted_misc2hle_retired.aborted_misc3hle_retired.aborted_misc4hle_retired.aborted_misc5rtm_retired.aborted_misc1rtm_retired.aborted_misc2rtm_retired.aborted_misc3rtm_retired.aborted_misc4rtm_retired.aborted_misc5fp_assist.x87_outputfp_assist.x87_inputfp_assist.simd_outputfp_assist.simd_inputmem_uops_retired.lock_loadsmem_uops_retired.lock_storesmem_uops_retired.split_loadsmem_uops_retired.split_storesmem_uops_retired.all_loadsmem_uops_retired.all_storesmem_load_uops_retired.hit_lfbl2_trans.demand_data_rdl2_trans.rfol2_trans.code_rdl2_trans.all_pfl2_trans.l1d_wbl2_trans.l2_filll2_trans.all_requestsl2_lines_in.il2_lines_in.sl2_lines_in.el2_lines_out.demand_cleanl2_lines_out.demand_dirtyuops_issued.sIngle_mulfp_comp_ops_exe.x87simd_fp_256.packed_singlesimd_fp_256.packed_doublearith.fpu_divl2_rqsts.rfo_hitsl2_store_lock_rqsts.missl2_store_lock_rqsts.hit_ml2_store_lock_rqsts.alll2_l1d_wb_rqsts.missl2_l1d_wb_rqsts.hit_el2_l1d_wb_rqsts.hit_ml2_l1d_wb_rqsts.alll1d_pend_miss.occurrencesidq.ms_dsb_activationsidq.all_dsb_uopsidq.all_mite_uopsbr_inst_exec.nontaken_condbr_inst_exec.taken_condbr_inst_exec.taken_direct_jmpbr_misp_exec.nontaken_condbr_misp_exec.taken_conddsb_fill.exceed_dsb_linesother_assists.avx_storebr_misp_retired.not_takenbr_misp_retired.takenl2_lines_out.pf_cleanl2_lines_out.pf_dirtyl2_lines_out.dirty_allld_blocks.data_unknownld_blocks.all_blockinsts_written_to_iq.instsl2_store_lock_rqsts.hit_el2_l1d_wb_rqsts.hit_shw_pre_req.dl1_missl1d.allocated_in_ml1d.evictionl1d.all_m_replacementbr_inst_exec.all_condbr_misp_exec.all_conddsb_fill.other_canceldsb_fill.all_canceluops_dispatched.threaduops_dispatched.coreagu_bypass_cancel.countsb_drain.anystore_blocks.at_retstore_blocks.l1d_blockdtlb_load_misses.anydtlb_load_misses.pde_missmem_inst_retired.loadsmem_inst_retired.storesmem_store_retired.dtlb_missuops_issued.stalled_cyclesuops_issued.fusedmem_uncore_retired.local_dramfp_comp_ops_exe.mmxfp_comp_ops_exe.sse_fpfp_comp_ops_exe.sse2_integerfp_comp_ops_exe.sse_fp_packedfp_comp_ops_exe.sse_fp_scalarsimd_int_128.packed_mpysimd_int_128.packed_shiftsimd_int_128.packsimd_int_128.unpacksimd_int_128.packed_logicalsimd_int_128.packed_arithsimd_int_128.shuffle_moveload_dispatch.rsload_dispatch.rs_delayedload_dispatch.mobload_dispatch.anyarith.mulinst_queue_writesinst_decoded.dec0two_uop_insts_decodedlsd_overflowl2_rqsts.ld_hitl2_rqsts.ld_missl2_rqsts.loadsl2_rqsts.rfosl2_rqsts.ifetch_hitl2_rqsts.ifetch_missl2_rqsts.ifetchesl2_rqsts.prefetch_hitl2_rqsts.prefetch_missl2_rqsts.prefetchesl2_data_rqsts.demand.i_statel2_data_rqsts.demand.s_statel2_data_rqsts.demand.e_statel2_data_rqsts.demand.m_statel2_data_rqsts.demand.mesil2_data_rqsts.prefetch.mesil2_data_rqsts.anyl2_write.rfo.i_statel2_write.rfo.s_statel2_write.rfo.m_statel2_write.rfo.hitl2_write.rfo.mesil2_write.lock.i_statel2_write.lock.s_statel2_write.lock.e_statel2_write.lock.m_statel2_write.lock.hitl2_write.lock.mesil1d_wb_l2.i_statel1d_wb_l2.s_statel1d_wb_l2.e_statel1d_wb_l2.m_statel1d_wb_l2.mesil3_lat_cache.missl3_lat_cache.referencel1d_cache_ld.i_statel1d_cache_ld.s_statel1d_cache_ld.e_statel1d_cache_ld.m_statel1d_cache_ld.mesil1d_cache_st.s_statel1d_cache_st.e_statel1d_cache_st.m_statel1d_cache_lock.hitl1d_cache_lock.s_statel1d_cache_lock.e_statel1d_cache_lock.m_statel1d_all_ref.anyl1d_all_ref.cacheabledtlb_misses.anydtlb_misses.walk_completeddtlb_misses.stlb_hitdtlb_misses.pde_missload_hit_prel1d_prefetch.requestsl1d_prefetch.missl1d_prefetch.triggersl1d.repll1d.m_repll1d.m_evictl1d.m_snoop_evictl1d_cache_lock_fb_hitio_transactionsl1i.hitsl1i.missesl1i.readslarge_itlb.hititlb_misses.anybr_inst_exec.condbr_inst_exec.directbr_inst_exec.non_callsbr_inst_exec.return_nearbr_inst_exec.direct_near_callbr_inst_exec.near_callsbr_inst_exec.takenbr_inst_exec.anybr_misp_exec.condbr_misp_exec.directbr_misp_exec.non_callsbr_misp_exec.return_nearbr_misp_exec.direct_near_callbr_misp_exec.near_callsbr_misp_exec.takenmacro_insts.fusions_decodedbaclear_force_iqlsd.cyclesuops_executed.port0uops_executed.port1uops_executed.port2_coreuops_executed.port3_coreuops_executed.port4_coreuops_executed.port5uops_executed.port015uops_executed.port234snoop_response.hitsnoop_response.hitesnoop_response.hitminst_retired.mmxuops_retired.anyuops_retired.macro_fusedmachine_clears.mem_ordermem_load_retired.dtlb_missfp_mmx_trans.to_fpfp_mmx_trans.to_mmxmacro_insts.decodeduops_decoded.msuops_decoded.esp_foldinguops_decoded.esp_synces_reg_renamesuop_unfusionbr_inst_decodedbpu_missed_call_retbaclear.clearbaclear.bad_targetbpu_clears.earlybpu_clears.latel2_transactions.loadl2_transactions.rfol2_transactions.ifetchl2_transactions.prefetchl2_transactions.l1d_wbl2_transactions.filll2_transactions.wbl2_transactions.anyl2_lines_in.s_statel2_lines_in.e_statel2_lines_in.anyl2_lines_out.prefetch_cleanl2_lines_out.prefetch_dirtyl2_lines_out.anyfp_assist.allfp_assist.outputfp_assist.inputsimd_int_64.packed_mpysimd_int_64.packed_shiftsimd_int_64.packsimd_int_64.unpacksimd_int_64.packed_logicalsimd_int_64.packed_arithsimd_int_64.shuffle_moveload_block.overlap_storemisalign_mem_ref.storeoffcore_requests.demand.rfooffcore_requests.any.readoffcore_requests.any.rfooffcore_requests.anysnoopq_requests.codesnoopq_requests.datasnoopq_requests.invalidateuops_decoded.stall_cyclesthread_activesq_misc.lru_hintsstore_forwards.goodsegment_reg_loads.anyprefetch.prefetcht0prefetch.sw_l2prefetch.prefetchntadata_tlb_misses.dtlb_miss_lddata_tlb_misses.dtlb_miss_stdata_tlb_misses.dtlb_missx87_comp_ops_exe.any.sx87_comp_ops_exe.any.arfp_assist.ardiv.sdiv.arl2_lines_inl2_m_lines_inl2_lines_outl2_m_lines_outl2_ldl2_stl2_lockl2_rqstsl2_rqsts.self.demand.i_statel2_rqsts.self.demand.mesil2_reject_busqeist_transthermal_tripl1d_cache.ldl1d_cache.stbus_request_outstandingbus_bnr_drvbus_trans_brdbus_trans_rfobus_trans_wbbus_trans_ifetchbus_trans_invalbus_trans_pwrbus_trans_pbus_trans_iobus_trans_defbus_trans_burstbus_trans_membus_trans_anyext_snoopicache.accessesitlb.missesitlb.flushmacro_insts.cisc_decodedmacro_insts.all_decodedsimd_uops_exec.ssimd_uops_exec.arsimd_sat_uop_exec.ssimd_sat_uop_exec.arsimd_uop_type_exec.mul.ssimd_uop_type_exec.shift.ssimd_uop_type_exec.pack.ssimd_uop_type_exec.unpack.ssimd_uop_type_exec.logical.ssimd_uop_type_exec.mul.arsimd_uop_type_exec.shift.arsimd_uop_type_exec.pack.arsimd_uop_type_exec.unpack.arsimd_uop_type_exec.logical.arbr_inst_retired.anybr_inst_retired.pred_takenbr_inst_retired.mispred_takenbr_inst_retired.mispredbr_inst_retired.takenbr_inst_retired.any1simd_inst_retired.vectorsimd_inst_retired.anyhw_int_rcvsimd_assistsimd_instr_retiredsimd_sat_instr_retiredbogus_brload_blockload_block.staload_block.stdload_block.until_retireload_block.l1dmisalign_mem_refsegment_reg_loadssse_pre_execsse_pre_exec.ntasse_pre_exec.l1sse_pre_exec.l2sse_pre_exec.storesdtlb_misses.miss_lddtlb_misses.l0_miss_lddtlb_misses.miss_stmemory_disambiguationmemory_disambiguation.successpage_walkspage_walks.countfp_comp_ops_exedelayed_bypassdelayed_bypass.fpdelayed_bypass.simdl1d_cache_ldl1d_cache_stl1d_cache_lockl1d_alll1d_all_refl1d_all.refl1d_all.cache_refl1d_repll1d_m_repll1d_m_evictl1d_pend_missl1d_splitl1d_split.loadsl1d_split.storessse_pre_misssse_pre_miss.ntasse_pre_miss.l1sse_pre_miss.l2l1d_prefetchcmp_snoopl1i_readsl1i_missesitlbitlb.small_missitlb.large_missbr_inst_execbr_missp_execbr_bac_missp_execbr_cnd_execbr_ind_execbr_ind_missp_execbr_ret_execbr_ret_missp_execbr_ret_bac_missp_execbr_call_execbr_ind_call_execbr_tkn_bubble_1br_tkn_bubble_2macro_instsespesp.synchesp.additionssimd_uops_execsimd_sat_uop_execsimd_uop_type_execsimd_uop_type_exec.mulsimd_uop_type_exec.shiftsimd_uop_type_exec.packsimd_uop_type_exec.unpacksimd_uop_type_exec.logicalsimd_uop_type_exec.arithmeticinst_retired.otherinst_retired.vm_hx87_ops_retiredx87_ops_retired.fxchx87_ops_retired.anyuops_retireduops_retired.ld_ind_bruops_retired.std_stauops_retired.macro_fusionuops_retired.fuseduops_retired.non_fusedmachine_nukesmachine_nukes.smcmachine_nukes.mem_orderbr_inst_retiredbr_inst_retired_mispredsimd_inst_retiredsimd_comp_inst_retiredmem_load_retiredmem_load_retired.l1d_missmem_load_retired.l2_line_missfp_mmx_transseg_reg_renamesseg_reg_renames.esseg_reg_renames.dsseg_reg_renames.fsseg_reg_renames.gsseg_reg_renames.anybaclearspref_rqsts_uppref_rqsts_dnL1-icache-loadsFR_retired_branches_mispredFR_retired_taken_branchesFP_dispatched_fpu_opsDC_refill_from_L2IC_refill_from_L2FR_taken_hardware_intrsL3_read_reqFP_dispatched_fpu_ops_ffLS_seg_reg_loadLS_uarch_resync_self_modifyLS_uarch_resync_snoopLS_retired_cflushLS_retired_cpuidDC_misaligned_data_refDC_uarch_late_cancel_accessDC_uarch_early_cancel_accessDC_dispatched_prefetch_instrDC_dcache_accesses_by_locksBU_memory_requestsBU_data_prefetchIC_uarch_resync_snoopIC_return_stack_hitIC_return_stack_overflowFR_retired_uopsFR_retired_far_ctl_transferFR_retired_resyncsFR_retired_near_retsFR_retired_near_rets_mispredFR_fpu_exceptionFR_num_brkpts_dr0FR_num_brkpts_dr1FR_num_brkpts_dr2FR_num_brkpts_dr3NB_cpu_io_to_mem_ioNB_cache_block_commandsFP_retired_sse_opsFP_retired_move_opsFP_retired_serialize_opsDC_copybackDC_1bit_ecc_error_foundDC_dtlb_L1_hitBU_system_read_responsesBU_octwords_written_to_systemBU_internal_L2_reqBU_fill_req_missed_L2BU_fill_into_L2IC_evictionIC_cache_lines_invalidateIC_itlb_reloadIC_itlb_reload_abortedFR_retired_mmx_sse_fp_instrNB_mem_ctrlr_page_accessNB_thermal_statusNB_sized_commandsNB_probe_results_upstream_reqNB_gart_eventsNB_ht_bus0_bandwidthNB_ht_bus1_bandwidthNB_ht_bus2_bandwidthNB_ht_bus3_bandwidthLS_smi_receivedLS_ineffective_prefetchLS_global_tlb_flushNB_mem_ctrlr_reqCB_cpu_to_dram_req_to_targetCB_io_to_dram_req_to_targetCB_cpu_req_to_target_0_to_7L3_l2_eviction_l3_fillL3_evictionFR_retired_fpu_instrNB_ECC_errorsNB_probe_resultNB_sized_blocksnode: 0x%016llx anc: 0x%016llx -- 0x%016llX: %s %s GNU %s binutils version %s Copyright (C) 2026 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later . This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. id=%d %s aux='%s' cmd='%s' user_name='%s' expr_spec='%s' %*c cond_spec='%s' val_spec='%s'%s %*c %*c unit='%s' unit_uname='%s' uname='%s' name='%s' (Cannot read %lld byte(s) offset=0x%llx) BinaryConstantPool[%d]: bad tag %d %s BaseMetricTreeNode* BaseMetricTreeNode::register_metric(BaseMetric*)/usr/src/debug/binutils/binutils-gdb/gprofng/src/BaseMetricTreeNode.ccJava Garbage Collection DurationCannot read class file %s (%s)Invalid expression in metric specification `%s' (MSTATE==%d)||(MSTATE==%d)||(MSTATE==%d)||(MSTATE==%d)(OMPSTATE>=0) && (MSTATE==%d) && ((1<=0 && ((1<::insert(long int, ITEM) [with ITEM = BaseMetric*]/usr/src/debug/binutils/binutils-gdb/gprofng/src/vec.hError: Invalid number entered: Error: Invalid number entered: %s Histable* DbeSession::createHistObject(Histable::Type)/usr/src/debug/binutils/binutils-gdb/gprofng/src/DbeSession.ccvoid Vector::insert(long int, ITEM) [with ITEM = DbeEA*]%s: Cannot read a local file header (%s offset=0x%lld%s: wrong local header signature ('%s' offset=%lld (0x%llx)%s: Cannot write %lld bytes (only %lld)%s: Cannot extract file %s (offset=0x%lld csize=%lld)%s: inflate('%s') error %d (%s)%s: cannot find the central directory record (fsize=%lld)%s: read failed (offset:0x%llx bytes:%lld%s: cannot find the central directory record%s: cannot find the Zip64 central directory record%s: cannot read the central directory record%s: cannot read the central file header (%lld (from %lld), offset=0x%016llx last=0x%016llx%s: wrong header signature (%lld (total %lld), offset=0x%016llx last=0x%016llxExperiment has warnings, see header for details Experiment has warnings, see experiment panel for details Has %d descendant(s), use commands controlling selection to load descendant data Has %d descendant(s), use filter panel to load descendant data ITEM Vector::remove(long int) [with ITEM = Countable*]int ccm_paramlist_index(COMPMSG_ID)Warning: improperly formatted compiler commentary message (%d parameters >= %d); please report this bug against the compiler Warning, improperly formatted compiler commentary message (parameter count mismatch = %d, param# = %d, msg_type = %x, `%s'); please report this bug against the compiler Warning, improperly formatted compiler commentary message (unexpected primitive type %d); please report this bug against the compiler Filtering HW Profile Address Data: %sHist_data* DataSpace::compute_metrics(MetricList*, Histable::Type, Hist_data::Mode, Histable*)/usr/src/debug/binutils/binutils-gdb/gprofng/src/DataSpace.cc!hist_data->find_hist_item (element)ITEM Vector::remove(long int) [with ITEM = ExpGroup*]SP_ANALYZER_DISCARD_TINY_EXPERIMENTSClock Profiling Interval, Microseconds((EXPGRID<<%llu) | (EXPID<<%llu))(IOHEAPBYTES==0?0:((IOHEAPBYTES<=(1<<0)?(1<<0):((IOHEAPBYTES<=(1<<2)?(1<<2):((IOHEAPBYTES<=(1<<4)?(1<<4):((IOHEAPBYTES<=(1<<6)?(1<<6):((IOHEAPBYTES<=(1<<8)?(1<<8):((IOHEAPBYTES<=(1<<10)?(1<<10):((IOHEAPBYTES<=(1<<12)?(1<<12):((IOHEAPBYTES<=(1<<14)?(1<<14):((IOHEAPBYTES<=(1<<16)?(1<<16):((IOHEAPBYTES<=(1<<18)?(1<<18):((IOHEAPBYTES<=(1<<20)?(1<<20):((IOHEAPBYTES<=(1<<22)?(1<<22):((IOHEAPBYTES<=(1<<24)?(1<<24):((IOHEAPBYTES<=(1<<26)?(1<<26):((IOHEAPBYTES<=(1<<28)?(1<<28):((IOHEAPBYTES<=(1<<30)?(1<<30):((IOHEAPBYTES<=(1<<32)?(1<<32):((IOHEAPBYTES<=(1<<34)?(1<<34):((IOHEAPBYTES<=(1<<36)?(1<<36):((IOHEAPBYTES<=(1<<38)?(1<<38):((IOHEAPBYTES<=(1<<40)?(1<<40):((IOHEAPBYTES<=(1<<42)?(1<<42):((IOHEAPBYTES<=(1<<44)?(1<<44):((IOHEAPBYTES<=(1<<46)?(1<<46):((IOHEAPBYTES<=(1<<48)?(1<<48):((IOHEAPBYTES<=(1<<50)?(1<<50):(IOHEAPBYTES==-1?-1:(1<<50|1)))))))))))))))))))))))))))))))))))))))))))))))))))))))((TSTAMP_HI-TSTAMP_LO)==0?0:(((TSTAMP_HI-TSTAMP_LO)<=1000?1000:(((TSTAMP_HI-TSTAMP_LO)<=10000?10000:(((TSTAMP_HI-TSTAMP_LO)<=100000?100000:(((TSTAMP_HI-TSTAMP_LO)<=1000000?1000000:(((TSTAMP_HI-TSTAMP_LO)<=10000000?10000000:(((TSTAMP_HI-TSTAMP_LO)<=100000000?100000000:(((TSTAMP_HI-TSTAMP_LO)<=1000000000?1000000000:(((TSTAMP_HI-TSTAMP_LO)<=10000000000?10000000000:(((TSTAMP_HI-TSTAMP_LO)<=100000000000?100000000000:(((TSTAMP_HI-TSTAMP_LO)<=1000000000000?1000000000000:(((TSTAMP_HI-TSTAMP_LO)<=10000000000000?10000000000000:(10000000000001))))))))))))))))))))))))(Not determined from the symbolic information provided by the compiler)(No identifying descriptor provided by the compiler)()(Dataspace data not requested during data collection)(Backtracking was prevented by a jump or call instruction)(Backtracking did not find trigger PC)(Could not determine VA because registers changed after trigger instruction)(Memory-referencing instruction did not specify a valid VA)Value_t StringMap::remove(const char*) [with Value_t = DbeJarFile*]/usr/src/debug/binutils/binutils-gdb/gprofng/src/StringMap.hValue_t StringMap::remove(const char*) [with Value_t = DbeFile*]id %6lld: [%4lld] parent = %6lld, offset = %+4lld %s basic_string: construction from null is not validITEM Vector::remove(long int) [with ITEM = Experiment*]pthread_create failed. errnum=%d (%s) End Segment %d -- %s -- %s ======END of mlist[%d] ========= void Vector::insert(long int, ITEM) [with ITEM = StringMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = StringMap::Entry*]ITEM Vector::remove(long int) [with ITEM = FilterSet*]ITEM Vector::remove(long int) [with ITEM = Vector*]No instruction frequency data available Instruction frequency data from experiment %s No index object type name has been specified.Index Object type name %s does not begin with an alphabetic characterIndex Object type name %s contains a non-alphanumeric characterMemory/Index Object type name %s is already definedNo index-expr has been specified.Index Object index expression is invalid: %sXXX setMetrics("%s") failed: %s void DbeView::add_subexperiment(int, bool)/usr/src/debug/binutils/binutils-gdb/gprofng/src/DbeView.ccvoid DbeView::add_experiment(int, bool)Address 0x%llx is out of bounds. Value_t DefaultMap::remove(Key_t) [with Key_t = long int; Value_t = Dwr_type*]/usr/src/debug/binutils/binutils-gdb/gprofng/src/DefaultMap.hvoid Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]Data not available for this filter selectionFunctions/Modules information corruptedNo selected object, bring up Functions Tab%s [%s] has an unrecognized op %d %s [%s] is a primitive metric void Vector::insert(long int, ITEM) [with ITEM = datatype_t*]void Vector::insert(long int, ITEM) [with ITEM = target_info_t*]DW_TAG_GNU_call_site_parameterDW_AT_MIPS_software_pipeline_depthDW_AT_GNU_exclusive_locks_requiredDW_AT_GNU_shared_locks_requiredDW_AT_GNU_call_site_data_valueDW_AT_GNU_call_site_target_clobberedDW_AT_GNU_all_source_call_sites# No GC events in experiment %d, %s (PID %d, %s) # %li events in experiment %d: %s (PID %d, %s) # exp:idx GC_start, GC_end, GC_duration %5d:%d, %3lld.%09lld, %3lld.%09lld, %3lld.%09lld %lld %-15s name='%s' parent=%lld next=%lld child=%lld dtype=%llx.%c0x%llx [ 0x%llx ] // Unable to determine target symbolHist_data* DbeView::get_hist_data(MetricList*, Histable::Type, int, Hist_data::Mode, Vector*, Histable*, Vector*, PathTree::PtreeComputeOption)Not a real function; no source or disassembly available.Source location not recorded in experimentObject name not recorded in experimentInvalid filter specification `%s' No Clock Profiling Packets in Experiment: %s Total Clock Profiling Packets: %d Experiment: %s #%6ld: %lld, %3lld.%09lld (%4lld.%09lld) t = %d, cpu = %d, frames = %d mstate = %d (%s), nticks = %d No Synctrace Packets in Experiment: %s Total Synctrace Packets: %d Experiment: %s synchronization object @ 0x%016llx; synchronization delay %3lld.%09lld No IO trace Packets in Experiment: %s Total IO trace Packets: %d Experiment: %s %s: fd = %d, ofd = %d, vfd = %lld, fstype = %d, rqst = %3lld.%09lld filename = `%s', nbytes = %d No HWC Profiling Packets in Experiment: %s Total HW Counter Profiling Packets: %d Experiment: %s #%6ld: %lld, %3lld.%09lld (%4lld.%09lld) t = %d, cpu = %d, frames = %d count = %10lld (0x%016llx), tag = %d (%s)%s va = 0x%016llx, pa = 0x%016llx No Heaptrace Packets in Experiment: %s Total Heaptrace Packets: %d Experiment: %s type = %d (%s), size = %llu (0x%llx), VADDR = 0x%016llx, OVADDR = 0x%016llx ERROR: unsupported disassembleITEM Vector::remove(long int) [with ITEM = Emsg*]ITEM Vector::remove(long int) [with ITEM = Experiment::ExperimentHandler::Element]%s: Bad experiment directory name%s: Data argument format error `%s'%s: [UNUSED] Bad clock-profiling argument%s: [UNUSED] Bad synchronization tracing argument%s: Bad hardware counter profiling argument%s: Experiment directory is not writeable; check umask and permissions%s: Turning on microstate accounting failed%s: Initializing clock-profiling failed%s: Initializing synchronization tracing failed%s: Initializing hardware counter profiling failed -- %s%s: HW counter data collection failed; likely cause is that another process preempted the counters%s: Experiment initialization failed, %s%s: Experiment size limit exceeded, writing %s%s: system name can not be determined%s: Can't read overview data for %s%s: Open of /dev/zero failed: %s%s: Mmap of /dev/zero failed: %s%s: Out of data handles for %s%s: Truncate failed for file %s%s: Initializing heap tracing failed%s: Initializing SIGPROF dispatcher failed%s: Initializing interval timer failed; %s%s: Initializing periodic sampling failed%s: Initializing MPI tracing failed%s: Initializing Java profiling failed%s: Initializing descendant process lineage failed%s: Out of disk space writing `%s'%s: Resetting interval timer failed: %s%s: Unable to create directory `%s'%s: JVM version with JVMTI requires more recent release of the performance tools; please upgrade%s: JVM version does not support JVMTI; no java profiling is available%s: JVM version does not support java callstacks; java mode data will not be recorded%s: Can't open dyntext file `%s'%s: Can't write dyntext file `%s'%s: Can't resolve map file `%s'%s: Initializing OpenMP tracing failed%s: Initializing experiment-duration setting to `%s' failed%s: Thread count exceeds maximum (%s); set SP_COLLECTOR_NUMTHREADS for higher value%s: Initializing IO tracing failed%s: No data was recorded in the experiment%s: Fatal error reported from DTrace -- %s%s: Seek error on map file `%s'%s: Unexpected value for founder `%s'%s: TSD could not be initialized%s: libcol_util.c initialization failed%s: Unable to cache mappings; internal error (`%s')%s: Experiment was written to a filesystem of type `%s'; data may be distorted%s: Profiling interval was changed from requested %s (microsecs.) used%s: Experiment size limit exceeded%s: SIGPROF handler was changed (%s) during the run; profile data may be unreliable%s: Periodic sampling rate adjusted %s microseconds%s: Application's attempt to set interval timer period to %s was ignored; its behavior may be changed%s: Collection interval timer period was changed (%s); profile data may be unreliable%s: SIGEMT handler was changed during the run; profile data may be unreliable%s: libcpc access blocked for hardware counter profiling%s: vfork(2) replaced by %s; execution may be affected%s: exec environment augmented with %s missing collection variables%s: target installed handler for sample signal %s; samples may be lost%s: target installed handler for pause/resume signal %s; data may be lost or unexpected%s: unable to reserve HW counters; data may be distorted by other users of the counters%s: application ran with a libthread version that may distort data; see collect(1) man page%s: Blocking %s ignored while in use for collection%s: Following disabled for uncollectable target (%s)%s: Following unqualified target may be unreliable (%s)%s: Imminent process ID change (%s) may result in an inconsistent experiment%s: Java profiling requires JVM version 1.4.2_02 or later%s: Collector reset application's profile timer %s; application behavior may be changed%s: Java heap profiling is not supported by JVMTI; disabled %s: Data race detection paused at %s because of running out of internal memory%s: Data race detection resumed%s: Too many concurrent/created threads; accesses with thread IDs above limit are not checked%s: The collector_thread_pause/collector_thread_resume APIs are deprecated, and will be removed in a future release%s: No profile data recorded in experiment%s: Linux libc sched_getcpu() not found; using x86 %s IDs rather than CPU IDsInitial execution directory `%s'Simulator dataspace profiling snap file `%s'%s: HWC overflow interval adjusted: %s%s: Actual deadlock detected; process terminated%s: Actual deadlock detected; process terminated and core dumped%s: Actual deadlock detected; process allowed to continueDwrCU::parse_cu_header: symbolsWarning: the section #%d (%s) is mismatch in ancillary file '%s') %s: the abbreviation code (%lld) does not match for the Dwarf entry (0x%llx) %s: the abbreviations table is corrupted (%lld <--> %lld) Cannot read ELF header of `%s'Load Object: '%s' (checksum Ox%lld). The .anc file '%s' has checksum Ox%llx ERROR: get_phdr(%d) failed ERROR: get_shdr(%d) failed *** Error: experiment %s version %d.%d is not supported; use the version of the tools that recorded the experiment to read it*** Note: experiment does not have events from idle CPUs*** Note: experiment does not have timestamps; timeline unavailable Data collection environment variable: %sXXX Unexpected setting found; %d attributes: *** Error: data parsing failed. Log file is corrupted.*** Warning: unrecognized element %s============================================================Implicit OpenMP Parallel RegionProcessing OpenMP Parallel Region Data: %s*** Warning: circular links in OMP regions; data may not be correct.OpenMP Task from Implicit Parallel RegionProcessing OpenMP Task Data: %s*** Warning: circular links in OMP tasks; data may not be correct.DataDescriptor* Experiment::get_hwc_events()/usr/src/debug/binutils/binutils-gdb/gprofng/src/Experiment.ccWarning: experiment %s has %.1f%%%% (%lld of %lld) dataspace events that were accepted without verification; data may be incorrect or misleading recompile with -xhwcprof and rerecord to get better data Warning: experiment %s has %.1f%%%% (%lld of %lld) dataspace events that could not be verified recompile with -xhwcprof and rerecord to get better data WARNING: Too many invalid HW counter profile events (%ld/%ld = %3.2f%%) in experiment %d (`%s'); data may be unreliable Clock-profiling, interval = %d microsecs. Synchronization tracing, threshold = %d microsecs. (calibrated); %s Synchronization tracing, threshold = %d microsecs.; %s HW counter-profiling (default); counters: HW counter-profiling; counters: %s, tag %d, interval %d, memop %d Follow descendant processes from: %s Data collection delay start %s seconds Data collection termination after %s secondsProcess pid %d, ppid %d, pgrp %d, sid %dCollector version: `%s'; experiment version %d.%d (%s)Host `%s', OS `%s', page size %d, architecture `%s' %d CPUs, with clocks ranging from %d to %d MHz.; max of %d MHz. assumed %d CPU%s, clock speed %d MHz. Memory: %d pages @ %d = %lld MB. Experiment start not recordedExperiment Ended: %ld.%09ld Data Collection Duration: %ld.%09ld*** Note: experiment was not closed*** Warning: Segment `%s' loaded with same address, size as `%s' [0x%llx-0x%llx] *** Warning: Segment %s [0x%llx-0x%llx] overlaps %s [0x%llx-0x%llx], which has been implicitly unloaded*** Error: log file in experiment cannot be read*** Error: log does not show target starting*** Error: log file in experiment could not be parsed*** Warning: system has variable clock frequency, which may cause variable execution times and inaccurate conversions of cycle counts into time.SAMPLE=%s (id=%d) MEMUSE=%lld TSTAMP=%lld ITEM Vector::remove(long int) [with ITEM = long long unsigned int]Value_t DefaultMap::remove(Key_t) [with Key_t = unsigned int; Value_t = Map*]Value_t DefaultMap::remove(Key_t) [with Key_t = unsigned int; Value_t = Map*]Value_t StringMap::remove(const char*) [with Value_t = SourceFile*]Value_t DefaultMap::remove(Key_t) [with Key_t = int; Value_t = long int]Value_t DefaultMap::remove(Key_t) [with Key_t = long int; Value_t = FileData*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap*>::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap*>::Entry*]Address Size (hex) Load time Unload time Checksum Name 0x%08llx %8lld (0x%08llx) %5lld.%09lld %5lld.%09lld "%s" 0123456789abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ-_void Vector::insert(long int, ITEM) [with ITEM = StringMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = Histable*]gprofng-archive: unable to copy `%s': %s gprofng-archive: cannot access file `%s': %s gprofng-archive: unable to open `%s': %s gprofng-archive: unable to write %d bytes to `%s': %s gprofng-archive: Internal error: path to common archive is NULL gprofng-archive: Internal error: file name in archive is NULL gprofng-archive: Internal error: file name is NULL gprofng-archive: Fatal error: pathconf(".", _PC_PATH_MAX) failed gprofng-archive: Fatal error: cannot determine current directory gprofng-archive: Fatal error: %s gprofng-archive: Fatal error: get_cksum(%s) returned %d gprofng-archive: Fatal error: pathconf(%s, _PC_PATH_MAX) failed gprofng-archive: file path is too long - truncated:%s gprofng-archive: Fatal error: pathconf(%s, _PC_NAME_MAX) failed gprofng-archive: file name is too long - truncated:%s gprofng-archive: Fatal error: cannot copy file %s to temporary file: %s gprofng-archive: Fatal error: rename(%s, %s) returned error: %d gprofng-archive: Fatal error: unable to allocate memory gprofng-archive: Fatal error: symlink(%s, %s) returned error: %d (errno=%s) Created symbolic link %s to file in common archive: %s gprofng-archive: Internal error: file does not exist in common archive: %s gprofng-archive: Fatal error: cannot copy file %s to common archive %s er_print: Experiment::readPacket: Error in data: src=%llx greater than %llx WARNING: There are %d invalid packet(s) in the %s fileint Experiment::read_dyntext_file()ITEM Vector::remove(long int) [with ITEM = Function*]*** Error: not a valid experiment name*** Error: experiment not found*** Error: experiment was recorded with an earlier version, and can not be readUnable to create directory `%s' void Experiment::resolve_frame_info(DataDescriptor*)*** Warning: %d frameinfo packets are missing from total of %d when resolving %s.DataDescriptor* Experiment::newDataDescriptor(int, int, DataDescriptor*)data_id >= 0 && data_id < DATA_LASTWarning: overview data file can't be readITEM Vector::remove(long int) [with ITEM = Sample*]Value_t DefaultMap2D::remove(Key1_t, Key2_t) [with Key1_t = unsigned int; Key2_t = long long int; Value_t = void*]/usr/src/debug/binutils/binutils-gdb/gprofng/src/DefaultMap2D.hValue_t DefaultMap2D::remove(Key1_t, Key2_t) [with Key1_t = unsigned int; Key2_t = long long int; Value_t = long unsigned int]Value_t StringMap::remove(const char*) [with Value_t = LoadObject*]Value_t DefaultMap::remove(Key_t) [with Key_t = long long int; Value_t = long unsigned int]Value_t IntervalMap::remove(Key_t) [with Key_t = long long int; Value_t = long unsigned int]/usr/src/debug/binutils/binutils-gdb/gprofng/src/IntervalMap.hValue_t DefaultMap::remove(Key_t) [with Key_t = long long int; Value_t = void*]Value_t IntervalMap::remove(Key_t) [with Key_t = long long int; Value_t = void*]Value_t DefaultMap::remove(Key_t) [with Key_t = LoadObject*; Value_t = int]ITEM Vector::remove(long int) [with ITEM = FilterNumeric::RangePair*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = IntervalMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = IntervalMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]Vector* PrUsage::getMstateValues()/usr/src/debug/binutils/binutils-gdb/gprofng/src/Exp_Layout.ccLMS_NUM_SOLARIS_MSTATES == states->size ()void Expression::copy(const Expression*)/usr/src/debug/binutils/binutils-gdb/gprofng/src/Expression.ccarg0 && v.next == &(rhs->arg0->v)Expression::Expression(const Expression&)arg0 && v.next == &(rhs.arg0->v)void Vector::insert(long int, ITEM) [with ITEM = StringMap::Entry*]virtual Histable* Function::convertto(Histable_type, Histable*)/usr/src/debug/binutils/binutils-gdb/gprofng/src/Function.ccValue_t DefaultMap::remove(Key_t) [with Key_t = long unsigned int; Value_t = HeapData*]virtual Histable* DbeEA::convertto(Histable::Type, Histable*)/usr/src/debug/binutils/binutils-gdb/gprofng/src/Hist_data.ccValue_t DefaultMap::remove(Key_t) [with Key_t = Histable*; Value_t = int]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DbeInstr*]virtual Histable* DbeLine::convertto(Histable::Type, Histable*)void Vector::insert(long int, ITEM) [with ITEM = PCInfo*]%s -- outline code from line %lld [%s]%s -- OMP parallel region from line %lld [%s]%s -- Parallel loop from line %lld [%s]%s -- OMP sections from line %lld [%s]%s -- OMP task from line %lld [%s]virtual Histable* DbeInstr::convertto(Histable::Type, Histable*)%s, line %u in alternate source context "%s"static int Hist_data::sort_compare(HistItem*, HistItem*, Sort_type, long int, Hist_data*)static int Hist_data::sort_compare_dlayout(const void*, const void*, const void*)ITEM Vector::remove(long int) [with ITEM = Hist_data::HistItem*]void Vector::insert(long int, ITEM) [with ITEM = Hist_data::HistItem*]xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx totalHeapActivity cannot process data due to wrong Histable (type=%d) 0x%016lx : type=%s(%d) id=%lld %s func=0x%016lx sourceFile=0x%016lx lineno=%lldValue_t DefaultMap::remove(Key_t) [with Key_t = void*; Value_t = FileData*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]Error: unable to read symbol table of %sError: unable to read load object file %sNote: checksum differs from that recorded in experiment for %sWarning: last-modified time differs from that recorded in experiment for %sTry running er_archive -F on the experiment, on the host where it was recordedError: Wrong version of archive for %sNote: no stabs or dwarf information in %sError: file %s is built for SPARC, and can't be read on IntelWarning: no libdwarf found to read DWARF symbol tablesNote: no DWARF symbol table in %sWarning: unexpected archive error %d../lib/analyzer/lib/machinemodelsid %6llu, @0x%llx sz-%lld %s (module = %s) id %6llu, @0x%llx - %s == alias of '%s' id %6llu, @0x%llx-0x%llx sz-%lldFunction* LoadObject::find_function(uint64_t)/usr/src/debug/binutils/binutils-gdb/gprofng/src/LoadObject.ccvoid Vector::insert(long int, ITEM) [with ITEM = Function*]No memory object name has been specified. Memory object `%s' is not defined. Machine model %s is already loaded Open of Machine model %s, file %s failed Warning: more than %d arguments to %s command, line %d Warning: extra arguments to %s command, line %d Error: missing arguments to %s command, line %d Unexpected command in machinemodel file %s on line %d: `%.64s' Process %llu, Thread %llu, JThread %llu '%s', Group '%s', Parent '%s' [ Group %llu, Process %llu, PID %llu ]Base Experiment %llu, Process %llu, PID %llu, %sNo memory object name has been specified.Memory Object type name %s does not begin with an alphabetic characterMemory Object type name %s contains a non-alphanumeric characterMemory Object index expression is invalid: %sIOActivity cannot process data due to wrong Histable (type=%d) %s has an unexpected checksum value;perhaps it was rebuilt. File ignoredUnexpected CP_LMS_USER metric subtype %dUnexpected CP_LMS_WAIT_CPU metric subtype %dUnexpected CP_LMS_USER_LOCK metric subtype %dUnexpected CP_LMS_SYSTEM metric subtype %dUnexpected LWT metric subtype %dExclusive Text Page Fault TimeInclusive Text Page Fault TimeAttributed Text Page Fault TimeUnexpected CP_LMS_TFAULT metric subtype %dExclusive Data Page Fault TimeInclusive Data Page Fault TimeAttributed Data Page Fault TimeUnexpected CP_LMS_DFAULT metric subtype %dUnexpected CP_KERNEL_CPU metric subtype %dUnexpected hwc %s metric subtype %dUnexpected derived %s metric subtype %dUnexpected Master Thread metric subtype %dUnexpected TOTAL metric subtype %dUnexpected LWCNT metric subtype %dUnexpected TOTAL_CPU metric subtype %dUnexpected CP_LMS_TRAP metric subtype %dExclusive Kernel Page Fault TimeInclusive Kernel Page Fault TimeAttributed Kernel Page Fault TimeUnexpected CP_LMS_KFAULT metric subtype %dUnexpected CP_LMS_SLEEP metric subtype %dUnexpected CP_LMS_STOPPED metric subtype %dUnexpected BYTES_MALLOCD metric subtype %dUnexpected MALLOCS metric subtype %dUnexpected BYTES_LEAKED metric subtype %dUnexpected LEAKS metric subtype %dUnexpected READ_BYTES metric subtype %dUnexpected WRITE_BYTES metric subtype %dUnexpected READCNT metric subtype %dUnexpected WRITECNT metric subtype %dUnexpected OTHERIOCNT metric subtype %dUnexpected IOERRORCNT metric subtype %dUnexpected READ_TIME metric subtype %dUnexpected WRITE_TIME metric subtype %dUnexpected OTHERIO_TIME metric subtype %dUnexpected IOERROR_TIME metric subtype %dUnexpected Non-OpenMP metric subtype %dExclusive OpenMP Overhead TimeInclusive OpenMP Overhead TimeAttributed OpenMP Overhead TimeUnexpected OpenMP Overhead metric subtype %dUnexpected OpenMP Work metric subtype %dExclusive OpenMP Implicit Barrier TimeInclusive OpenMP Implicit Barrier TimeAttributed OpenMP Implicit Barrier TimeUnexpected OpenMP Implicit Barrier metric subtype %dExclusive OpenMP Explicit Barrier TimeInclusive OpenMP Explicit Barrier TimeAttributed OpenMP Explicit Barrier TimeUnexpected OpenMP Explicit Barrier metric subtype %dUnexpected OpenMP Wait metric subtype %dUnexpected OpenMP Slave Idle metric subtype %dExclusive OpenMP Reduction TimeInclusive OpenMP Reduction TimeAttributed OpenMP Reduction TimeUnexpected OpenMP Reduction metric subtype %dExclusive OpenMP Lock Wait TimeInclusive OpenMP Lock Wait TimeAttributed OpenMP Lock Wait TimeUnexpected OpenMP Lock Wait metric subtype %dExclusive OpenMP Critical Section Wait TimeInclusive OpenMP Critical Section Wait TimeAttributed OpenMP Critical Section Wait TimeUnexpected OpenMP Critical Section Wait metric subtype %dExclusive OpenMP Ordered Section Wait TimeInclusive OpenMP Ordered Section Wait TimeAttributed OpenMP Ordered Section Wait TimeUnexpected OpenMP Ordered Section Wait metric subtype %dExclusive OpenMP Master Serial TimeInclusive OpenMP Master Serial TimeAttributed OpenMP Master Serial TimeUnexpected OpenMP Master Serial metric subtype %dExclusive OpenMP Single Region TimeInclusive OpenMP Single Region TimeAttributed OpenMP Single Region TimeUnexpected OpenMP Single Region metric subtype %dExclusive OpenMP Ordered Region TimeInclusive OpenMP Ordered Region TimeAttributed OpenMP Ordered Region TimeUnexpected OpenMP Ordered Region metric subtype %dUnexpected Race Access metric subtype %dUnexpected Deadlocks metric subtype %dInvalid metric specification: %s inapplicable for data metrics Invalid metric specification: %s inapplicable for index metrics Invalid metric specification: %s applicable for caller-callee metrics only Invalid metric specification: %s applicable for data-derived metrics only Inclusive, Exclusive, or Data metrics cannot be specified for caller-callee sort: %s Inclusive, Exclusive, or Attributed metrics cannot be specified for data-derived sort: %s Inclusive, Data or Attributed metrics cannot be specified for index sort: %s Data or Attributed metrics cannot be specified for sort: %s Invalid sort specification: %s Invalid caller-callee sort specification: %s Invalid data-derived sort specification: %s Invalid index sort specification: %s Invalid I/O sort specification: %s Invalid heap sort specification: %s %s %*c subtype=%d time_val=%d vis=%d tvis=%d pvis=%d %*c abbr='%s' cmd='%s' name='%s' Object file `%s.class' not readableError reading line-number information in object `%s'; source annotation not availableError reading symbol table in object `%s'; disassembly annotation not availableWarning! Source file `%s' is newer than the experiment dataWarning! Object file `%s' is newer than the experiment dataWarning! Object file `%s' is not the same one that was linked into executable. Object file: `%s' compiled on: %s Executable contains object file compiled on: %sNo data recorded to support metric specification: %s Metric specification for `%s' has appeared before in %sITEM Vector::remove(long int) [with ITEM = Metric*]No valid metrics specified in `%s' NULL metric list can not be printed; abortingmetric list is empty; aborting metriclist at 0x%lx: %s, %lld metrics; sort by %s [st %2d, VT %d, vis = %4s, T=%d, sort = %c]Fatal: no name metric in Module::computeMetrics mlist: void Vector::insert(long int, ITEM) [with ITEM = long int]`%s' is a native method; byte code not available PathTree processing experiment %d (`%s'); duration %lld.%06lld Processed %ld clock-profile events (%3.2f/sec.) Processed %ld clock-profile eventsWARNING: too few clock-profile events (%ld) in experiment %d (`%s') for statistical validity Processed %ld synctrace events Processed %ld IO trace events Processed %ld hwc-profile events (%3.2f/sec.) Processed %ld hwc-profile eventsWARNING: too few HW counter profile events (%ld) in experiment %d (`%s') for statistical validity Processed %ld heaptrace events Processed %ld race access eventsPathTree time = %lld.%06lld CPU-time %lld.%06lld void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]Value_t DefaultMap::remove(Key_t) [with Key_t = Function*; Value_t = long int]%s %s (0x%08llx) -- ndesc = %lld Number of nodes: %d, total size: %d n = %lld, dn = %lld, MD = %lld (/usr/bin/lp -c -n%d %s) 2>/dev/null 1>&2(/usr/bin/lp -c -d%s -n%d %s) 2>/dev/null 1>&2Error: empty temporary file: %s Error: cannot open temporary file: %s Error: cannot read temporary file: %s Process With Highest Peak Memory Usage ------------------------------------------------------- Heap size bytes %lld Experiment Id %d Process Id %d Time of peak %.3f (secs.) Memory Allocations Statistics Allocation Size Range Allocations 0KB - 1KB %d 1KB - 8KB %d 8KB - 32KB %d 32KB - 128KB %d 128KB - 256KB %d 256KB - 512KB %d 512KB - 1000KB %d 1000KB - 10MB %d 10MB - 100MB %d 100MB - 1GB %d 1GB - 10GB %d 10GB - 100GB %d 100GB - 1TB %d 1TB - 10TB %d Smallest allocation bytes %lld Largest allocation bytes %lld Total allocations %d Total bytes %lld Leak Size Range Leaks Smallest leaked bytes %lld Largest leaked bytes %lld Total leaked %d I/O Size Range Write Calls 1GB - 10GB %d 10GB - 100GB %d 100GB - 1TB %d 1TB - 10TB %d Longest write %.6f (secs.) Smallest write bytes %lld Largest write bytes %lld Total time %.6f (secs.) Total calls %d I/O Size Range Read Calls ------------------------------------------------------ Longest time %.6f (secs.) Smallest read bytes %lld Largest read bytes %lld ----------------------------------------------------- Total calls %d There is no heap event information in the experiments There is no IO event information in the experiments Aggregated statistics for selected samples---------------------------------------------------------------- Dataobjects sorted by metric: No dataspace information recorded in experiments Source file: %s Object file: %s Load Object: %s INTERNAL ERROR: missing line textCallers and callees sorted by metric: Error: Specified item `%s' had no recorded metrics. Functions sorted by metric: %s Dataobjects sorted by metric: %s Objects sorted by metric: %s No leak or allocation information recorded in experiments e.heapleakbytes:e.heapleakcnt:nameSummary Results: Distinct Leaks = %d, Total Instances = %lld, Total Bytes Leaked = %lld Leak #%d, Instances = %lld, Bytes Leaked = %lld e.heapallocbytes:e.heapalloccnt:nameSummary Results: Distinct Allocations = %d, Total Instances = %lld, Total Bytes Allocated = %lld Allocation #%d, Instances = %lld, Bytes Allocated = %lld Value_t DefaultMap::remove(Key_t) [with Key_t = int; Value_t = DbeLine*]Value_t DefaultMap::remove(Key_t) [with Key_t = Function*; Value_t = Function*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*].th_C { text-align:center; background-color:lightgoldenrodyellow; } .th_CG { text-align:center; background-color:#ffff33; } .th_L { text-align:left; background-color:lightgoldenrodyellow; } .th_LG { text-align:left; background-color:#ffff33; } .td_R { text-align:right; } .td_RG { text-align:right; background-color:#ffff33; } .td_LG { text-align:left; background-color:#ffff33; }
ITEM Vector::remove(long int) [with ITEM = Histable*]DefaultHandler::startElement qName='%s' char* SourceFile::getLine(int)/usr/src/debug/binutils/binutils-gdb/gprofng/src/SourceFile.ccError: No function or file has been specified. Error: %s is not a real function; no source or disassembly available. Error: No source or disassembly available for hidden object %s. Error: Source file context %s does not contribute to function `%s'. Error: No function with given name `%s %s' found. Error: No function or file with given name `%s' found. Error: Object name not recorded in experiment Error: Source location not recorded in experiment The argument to '%s' must be '%s' or '%s' or a single-characterPathmap can have neither from nor to as NULL Pathmap from must differ from to Pathmap from `%s' to `%s' already exists %s: Can read only %lld bytes instead %lldWrong line number %d. '%s' has only %d linesNo commentary classes has been specified.Ambiguous commentary classes: Invalid argument for commentary classes: Out of range commentary classes argument: Available commentary classes: Processed %s for default settingsProcessed system gprofng.rc file for default settings .er.rc:%d The argument of 'compare' should be 'on', 'off', 'delta', or 'ratio' Unrecognized .gprofng.rc command on line %d: `%.64s'Warning: Default gprofng.rc file (%s) missing; configuration error ITEM Vector::remove(long int) [with ITEM = Include::SrcFileInfo*]Value_t StringMap::remove(const char*) [with Value_t = Symbol*]virtual void* DataINT32::fetchObject(long int)/usr/src/debug/binutils/binutils-gdb/gprofng/src/Table.ccvirtual void DataINT32::setObjValue(long int, void*)virtual void* DataUINT32::fetchObject(long int)virtual void DataUINT32::setObjValue(long int, void*)virtual void* DataINT64::fetchObject(long int)virtual void DataINT64::setObjValue(long int, void*)virtual void* DataUINT64::fetchObject(long int)virtual void DataUINT64::setObjValue(long int, void*)virtual int DataOBJECT::fetchInt(long int)virtual long long unsigned int DataOBJECT::fetchULong(long int)virtual long long int DataOBJECT::fetchLong(long int)virtual double DataOBJECT::fetchDouble(long int)virtual void DataOBJECT::setValue(long int, uint64_t) ======= Stabs::dump: %s ========= ===== END of Stabs::dump: %s ========= Stats_data::Stats_item Stats_data::fetch(int)/usr/src/debug/binutils/binutils-gdb/gprofng/src/Stats_data.ccindex >= 0 && index < stats_items->size ()Process-wide Resource UtilizationJava Garbage Collection Eventsvoid checkCompatibility(VType_type, VType_type)v2 == TYPE_INT32 || v2 == TYPE_UINT32v2 == TYPE_INT64 || v2 == TYPE_UINT64Loop below is serial, but parallelizable: Loop below is not parallelized: compiler generated two versions of this loopthe variable(s) "%s" cause a data dependency in this looploop was significantly transformed during optimizationloop may or may not hold enough work to be profitably parallelizedloop was marked by user-inserted pragmaloop contains I/O, or other function calls, that are not MT safeloop contains backward flow of controlloop may have been distributedtwo loops or more may have been fusedtwo or more loops may have been interchangedIn the call below, parameter number %d caused a copy-in -- loop(s) insertedIn the call below, parameter number %d caused a copy-out -- loop(s) insertedIn the call below, parameter number %d caused a copy-in and a copy-out -- loops insertedvoid Vector::insert(long int, ITEM) [with ITEM = StringMap::Entry*]QL::Parser::value_type::~value_type()QL::Parser::symbol_type::symbol_type(int)tok == token::L_YYEOF || (token::L_YYerror <= tok && tok <= token::L_FILEIOVFD) || (token::L_IN <= tok && tok <= 317)T& QL::Parser::value_type::as() [with T = Expression*]T& QL::Parser::value_type::as() [with T = long unsigned int]T& QL::Parser::value_type::as() [with T = std::__cxx11::basic_string]void Vector::insert(long int, ITEM) [with ITEM = long long int]constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::operator[](size_type) [with _Tp = QL::Parser::stack_symbol_type; _Alloc = std::allocator; reference = QL::Parser::stack_symbol_type&; size_type = long unsigned int]/usr/include/c++/16/bits/stl_vector.hT& QL::Parser::value_type::emplace(U&& ...) [with T = std::__cxx11::basic_string; U = {std::__cxx11::basic_string, std::allocator >}]Multiline strings are not supportedITEM Vector::remove(long int) [with ITEM = long int]T& QL::Parser::value_type::emplace(U&& ...) [with T = Expression*; U = {Expression*}]T& QL::Parser::value_type::emplace(U&& ...) [with T = long unsigned int; U = {long unsigned int}]constexpr std::vector<_Tp, _Alloc>::reference std::vector<_Tp, _Alloc>::back() [with _Tp = QL::Parser::stack_symbol_type; _Alloc = std::allocator; reference = QL::Parser::stack_symbol_type&]constexpr void std::vector<_Tp, _Alloc>::pop_back() [with _Tp = QL::Parser::stack_symbol_type; _Alloc = std::allocator]tmpView->getSize () == newSizevoid DataView::sort(const int*, int)prop_count >= 0 && prop_count < MAX_SORT_DIMENSIONSvoid DataView::setFilter(FilterExp*)T& QL::Parser::value_type::emplace(U&& ...) [with T = Expression*; U = {}]T& QL::Parser::value_type::emplace(U&& ...) [with T = std::__cxx11::basic_string; U = {}]T& QL::Parser::value_type::emplace(U&& ...) [with T = long unsigned int; U = {}]void Vector::insert(long int, ITEM) [with ITEM = JThread*]Experiment is active; command ignored. Can not determine CPU clock frequency. System clock profile resolution can not be determined. Java arguments can not be set if Java profiling is not enabled. Count data cannot be collected along with any other data. Count data cannot be collected with any of -F -S -y -l -j -J -x -t . -I or -N can only be specified with count data. void Vector::insert(long int, ITEM) [with ITEM = Experiment::MapRecord*]void TValue::make_delta(TValue*, TValue*)/usr/src/debug/binutils/binutils-gdb/gprofng/src/util.ccvoid TValue::make_ratio(TValue*, TValue*)Warning: Clock profiling timer reset from %.3f millisec. to %.3f millisec. as required by profiling driver Unrecognized synchronization tracing threshold `%s' Incorrect range in heap trace parameter '%s' Unrecognized heap tracing parameter `%s' Unrecognized I/O tracing parameter `%s' Unrecognized count parameter `%s' time parameter can not be NULL Unrecognized time parameter `%s' Invalid time parameter `%s': start time must be earlier than end time Specified PID can not be NULL Unrecognized sample period `%s' Directory (%s) for group file %s is not writeable: %s Group file %s is not writeable: %s Timed out: waiting for group file %s Can't create group file %s: %s Can't initialize group file %s gprofng was built without support for profiling Java applications Java-profiling parameter is neither "on", nor "off", nor is it a directory: `%s' char* Coll_Ctrl::set_follow_mode(const char*)/usr/src/debug/binutils/binutils-gdb/gprofng/src/collctrl.ccUnrecognized follow-mode parameter `%s' Unrecognized profiling idle cpus parameter `%s' Unrecognized archive-mode parameter `%s' Signal %s (%d) can not be used for both sample and pause-resume (delayed initialization) Signal %d can not be used for both sample and pause-resume (delayed initialization) Invalid pause-resume (delayed initialization) signal %d name %s is in use and cannot be updated name %s is in use; changed to %s Store directory %s is not writeable: %s collect: Internal error: loop count achievedUnable to create directory `%s' -- %s %s: %d Unable to create directory `%s' -- %s Invalid pause/resume signal %d Warning: clock-based memoryspace and dataspace profiling is no longer supported Unrecognized clock-profiling interval `%s' Warning: Clock profiling at %.3f millisec. interval is not supported on this system; minimum %.3f millisec. used Clock profiling at %.3f millisec. interval is not supported on this system; maximum %.3f millisec. used Clock profile interval rounded from %.3f to %.3f (system resolution = %.3f) millisec. clock profiling enabled, %.3f millisec. synchronization tracing enabled, threshold: calibrate; synchronization tracing enabled, threshold: all; synchronization tracing enabled, threshold: %d micros.; ERR -- unexpected synctrace_scope %d hardware counter profiling (default) enabled: hardware counter profiling enabled: static count data will be generated (for a.out only) descendant processes will be followed experiments will be recorded for descendant processes that match pattern '%s' descendant processes will all be followed descendant processes will not be followed following descendant processes: pause-resume (delayed initialization) signal %s (%d) -- paused pause-resume (delayed initialization) signal %s (%d) pause-resume (delayed initialization) signal %d -- paused pause-resume (delayed initialization) signal %d data-collection duration, %d- secs. data-collection duration, %d-%d secs. data-collection duration, %d secs. experiment size limit %d MB. no experiment size limit set host: `%s', ncpus = %d, clock frequency %d MHz. memory: %ld pages @ %ld bytes = %lld MB. Creating experiment directory %s (Process ID: %ld) ... Creating experiment directory %s (Process ID: %ld) ... No default HW counter set is defined for %s HW counter set for %s cannot be loaded on this system HW counter set for %s, "%s", format error %d:%d:%lld:%lld:%s:%s:%lld:%d:m%lld:%d:%d:0x%xNote: Heap profiling will only trace native allocations, not Java allocations. Warning: No function level data requested; only statistics will be collected. Store directory %s is not accessible: %s Warning: Experiment name is an absolute path; directory name %s ignored. Experiment name `%s' must end in `.er' /bin/rm -rf %s >/dev/null 2>&1Cannot remove experiment `%s' Experiment group name `%s'must end in `.erg' Starting %s %ld.%09ld, exp %s.er, "%s"Starting %s %ld.%09ld, no experiment, "%s"Started %s %ld.%09ld, exp %s.er, "%s"Started %s %ld.%09ld, no experiment, "%s"*** Error: HW counter tag %d out of range [%d - %d]; ignored*** Error: Duplicate HW counter tag %d specified; ignored*** Error: Cannot find kernel module symbols file %s; ignoredValue_t StringMap::remove(const char*) [with Value_t = int]void Vector::insert(long int, ITEM) [with ITEM = StringMap::Entry*]*** Warning: Error opening file for reading: %sError: symlink(%s, %s) returned error: %d dbeSetPathmaps: size of 'from' does not match for size of 'to' Start Time : %s Duration : %0.3f Seconds Error: Cannot open directory Error: cannot remove %s - not a regular file and not a directory Error: file size is greater than the limit (%d bytes) Vector* dbeGetRefMetricTreeValues(int, Vector*, Vector*)/usr/src/debug/binutils/binutils-gdb/gprofng/src/Dbe.cccycleValues->size () == ngroupsvoid Vector::insert(long int, ITEM) [with ITEM = long unsigned int]Function, line # in "sourcefile"Please enter the name of the file to which to printNo source or disassembly available for hidden objectUnable to submit print request toVector* dbeGetSummary(int, Vector*, int, int)strcmp (mvec->fetch (index2)->get_cmd (), mitem->get_cmd ()) == 0void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap*>::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]void Vector::insert(long int, ITEM) [with ITEM = DefaultMap::Entry*]Vector* dbeGetTLData(int, int, int, int, int, int, hrtime_t, hrtime_t, int, bool, Vector*)Vector* dbeGetAggregatedValue(int, char*, char*, char*, hrtime_t, hrtime_t, int, char*, char*)kill of process %d not supported Process With Highest Peak Memory UsageValue_t DefaultMap::remove(Key_t) [with Key_t = long long int; Value_t = long int]Value_t DefaultMap::remove(Key_t) [with Key_t = long long int; Value_t = long long int]Value_t DefaultMap::remove(Key_t) [with Key_t = long unsigned int; Value_t = Vector*]Value_t DefaultMap::remove(Key_t) [with Key_t = Function*; Value_t = int]Value_t DefaultMap::remove(Key_t) [with Key_t = long unsigned int; Value_t = int]mem_inst_retired.latency_above_thresholdSee Chapter 10 of the "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD Opteron Processors," AMD publication #26094See section 3.15 of the "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors," AMD publication #31116See Chapter 19 of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2" Order Number: 253669-047US, June 2013See Chapter 19 of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide"See Chapter 19 of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide, Part 2" Order Number: 253669-045US, January 2013Intel Arch PerfMon v%d on Family %d Model %d%s: address size has unexpected value of %u %s: %s: unexpected end of file %s: dimension unit changed between histogram records %s: from '%s' %s: to '%s' %s: dimension abbreviation changed between histogram records %s: from '%c' %s: to '%c' %s: different scales in histogram records: %f != %f %s: found a symbol that covers several histogram records%s: overlapping histogram records %s: %s: unexpected EOF after reading %u of %u samples [arc_lookup] parent == 0 || child == 0%s: %s: not in executable format %s: can't find .text section in %s %s: warning: ignoring basic-block exec counts (use -l or --line) %s: file too short to be a gmon file %s: file `%s' has bad magic cookie %s: file `%s' has unsupported version %d %s: %s: found bad tag %d (file corrupted?) %s: don't know how to deal with file format %d Too many attributes defined in `%s'Missing value for attribute `%s' in `%s'Illegal value for attribute `%s' in `%s'out of memory, could not parse attributes for `%s', allowable umask bits are: 0x%llx `%s' attribute `%s' could not be set to 0x%llx More than %d counters were specified Data descriptor syntax error near `%s' Negative interval specified for HW counter `%s' HW counter profiling is disabled unless only one logical CPU per HyperThreaded processor is online (see psradm) The HW counter configuration could not be loaded: %s%sThe HW counter configuration could not be loaded Run "%s -h" with no other arguments for more information on HW counters on this system. Clock rate = %d MHz (from reading /proc/cpuinfo) %d CPUs Clock rate = %d MHz (set by default) %d CPUs libcpc cannot identify processor type Analyzer CPU table is invalid No HW counters were specified.HW counter profiling is not supported on this system: %s%sHW counter profiling is not supported on this system HW counter profiling is not supported on '%s' `+' may not be correctly supported on `%s' because processor is not recognized.Warning: `-' is not supported on `%s' -- memory reference backtracking will remain enabled for this counter Warning: `+' is not supported on `%s' -- memory reference backtracking will not be enabled for `%s' Warning: `+' is not supported on `%s' -- memory reference backtracking will not be enabled for this counter Warning: HW counter `%s' is not program-related -- callstacks will be not be recorded for this counter Invalid attribute specified for counter `%s': %s Duplicate attribute specified for counter `%s': %s Invalid interval for HW counter `%s': %s No HW counters were specified. The HW counter configuration could not be loaded: More than %d counters were specified The number of HW counters specified exceeds internal resources Specifying HW counters on `%s' (cpuver=%d): turn on default set of HW counters at the specified rate specify HW counter profiling for one HW counter only -h [-h ]... -h [,]... specify HW counter profiling for up to %u HW counters Specifying HW counters on `%s' (cpuver=%d) Hardware counter profiling is supported for only one counter. Hardware counter profiling is supported for up to %u HW counters. == %s%s,[] must be selected from the available counters listed below. On most systems, if a counter is not listed below, it may still be specified by its numeric value. Counters labeled as 'memoryspace' in the list below will collect memoryspace data by default. optional attribute where can be in decimal or hex format, and can be one of: Multiple attributes may be specified, and each must be preceded by a ~. Optional attribute where can be in decimal or hex format, and can be one of: == {auto|lo|on|hi} `auto' (default) match the rate used by clock profiling. If clock profiling is disabled, use `on'. `lo' per-thread maximum rate of ~10 samples/second `on' per-thread maximum rate of ~100 samples/second `hi' per-thread maximum rate of ~1000 samples/second == Fixed event interval value to trigger a sample. Smaller intervals imply more frequent samples. Example: when counting cycles on a 2 GHz processor, an interval of 2,000,003 implies ~1000 samples/sec Use this feature with caution, because: (1) Frequent sampling increases overhead and may disturb other applications on your system. (2) Event counts vary dramatically depending on the event and depending on the application. (3) A fixed event interval disables any other gprofng internal mechanisms that may limit event rates. Guidelines: Aim at <1000 events per second. Start by collecting with the 'hi' option; in the experiment overview, notice how many events are recorded per second; divide by 1000, and use that as your starting point. A comma ',' followed immediately by white space may be omitted. Other attributes may be supported by the chip, but are not supported by DTrace and will be ignored by er_kernel. Multiple attributes may be specified. / forces use of a specific hardware register. (Solaris only) If not specified, %s will attempt to place the counter into the first available register and as a result may be unable to place subsequent counters due to register conflicts. The / in front of the register number is required if a register is specified. No default HW counter set defined for this system. The default HW counter set (%s) defined for %s cannot be loaded on this system. Aliases for most useful HW counters: While the above aliases represent the most useful hardware counters for this processor, a full list of raw (unaliased) counter names appears below. First is an overview of some of these names. == Cycles. Count active cycles with Cycles_user Set attributes to choose user, system, and/or hyperprivileged cycles. == Instructions. Count instructions when they are committed with: It is the total of these counters: Branches %s Floating Point and Graphics Unit Instr_FGU_crypto %s Instr_ld %s Instr_st %s basic arithmetic and logical instructions Instr_other %s Some subsets of these instructions can be counted separately: Br_taken %s SW Count instructions (counts special no-op assembler instructions) == Commit. Instructions may be launched speculatively, executed out of order, etc. We can count the number of cycles during which 0, 1, or 2 instructions are actually completed and their results committed: %s %s %s %s %s is a useful way of identifying parts of your application with high-latency instructions. == Cache/memory hierarchy. In the cache hierarchy: * Each socket has memory and multiple SPARC core clusters (scc). * Each scc has an L3 cache and multiple L2 and L1 caches. Loads can be counted by where they hit on socket: hit neighbor scc (same socket)miss all caches (same socket) These loads can also be grouped: DC_miss_nbr_scc_hit + DC_miss_nbr_scc_miss Loads that miss all caches on this socket can be counted: hit local memory (same socket)hit remote memory (off socket) These events are for speculative loads, launched in anticipation of helping performance but whose results might not be committed. To count only data-cache misses that commit, or for memoryspace profiling, use the 'memoryspace' counter: == TLB misses. The Translation Lookaside Buffer (TLB) is a cache of virtual-to-physical page translations. If a virtual address (VA) is not represented in the TLB, an expensive hardware table walk (HWTW) must be conducted. If the page is still not found, a trap results. There is a data TLB (DTLB) and an instruction TLB (ITLB). TLB misses can be counted by: DTLB_HWTW_search ITLB_HWTW_search or broken down by page size: DTLB_HWTW_hit_8K ITLB_HWTW_hit_8K DTLB_HWTW_hit_64K ITLB_HWTW_hit_64K DTLB_HWTW_hit_4M ITLB_HWTW_hit_4M DTLB_HWTW_hit_256M ITLB_HWTW_hit_256M DTLB_HWTW_hit_2G_16G ITLB_HWTW_hit_2G_16G DTLB_HWTW_miss_trap ITLB_HWTW_miss_trap == Branch misprediction. Count branch mispredictions with: Br_mispred It is the total of: Br_dir_mispred direction was mispredicted %s target was mispredicted == RAW hazards. A read-after-write (RAW) delay occurs when we attempt to read a datum before an earlier write has had time to complete: RAW_hit_st_q~emask=0xf The mask 0xf counts the total of all types such as: RAW_hit_st_buf write is still in store buffer RAW_hit_st_q write is still in store queue == Flush. One can count the number of times the pipeline must be flushed: load missed L3 and >1 strand is active on the coreSPARC exceptions and trap entry/returnstate change to/from halted/paused Some subsets of instructions can be counted separately: We can count the number of cycles during which no instructions were able to commit results using: %s %s is a useful way of identifying parts of your application with high-latency instructions. In the cache hierarchy: * Each processor has 4 memory controllers and 2 quad core clusters (QCC). * Each QCC contains 4 cache processor clusters (CPC). * Each CPC contains 4 cores. * Each core supports 8 hardware threads. * The L3 consists of 2 partitions with 1 QCC per partition. hit own L3 but require copyback from L2DDTLB_HWTW ITLB_HWTWDTLB_fill_8KB ITLB_fill_8KB DTLB_fill_64KB ITLB_fill_64KB DTLB_fill_4MB ITLB_fill_4MB DTLB_HWTW_hit_256M ITLB_HWTW_hit_256M DTLB_HWTW_hit_16G ITLB_HWTW_hit_16G DTLB_HWTW_hit_1T ITLB_HWTW_hit_1T TLB traps, which can require hundreds of cycles, can be counted with: DTLB_fill_trap ITLB_fill_trap RAW_hit events can be broken down into: Total data-cache misses can be counted with: DC_miss DC_miss_nospec They are the totals of misses that hit in L2/L3 cache, local memory, or remote memory: DC_miss_L2_L3_hit DC_miss_L2_L3_hit_nospec DC_miss_local_hit DC_miss_local_hit_nospec DC_miss_remote_L3_hit DC_miss_remote_L3_hit_nospec The events in the left column include speculative operations. Use the right-hand _nospec events to count only data accesses that commit or for memoryspace profiling. DTLB_miss_asynch ITLB_miss_asynchDTLB_fill_256MB ITLB_fill_256MB DTLB_fill_2GB ITLB_fill_2GB DTLB_fill_trap ITLB_fill_trapjavax.xml.parsers.SAXParserFactoryStalled Cycles during retirement.The Instruction TLB Load MissesInstruction decoder corrects the predicted target and resteers thebranch predictorDynamic indirect predictions (branch used the indirect predictor tomake a prediction)L2 branch prediction overrides existing prediction (speculative)Retired branch instructions (all types of architectural control flowchanges, including exceptions and interrupts)Retired far control transfers (far call/jump/return, IRET, SYSCALL andSYSRET, plus exceptions and interrupts). Far control transfers are notsubject to branch predictionRetired indirect branch instructions mispredicted (only EXmispredicts). Each misprediction incurs the same penalty as amispredicted conditional branch instructionRetired branch instructions mispredictedRetired taken branch instructions (all types of architectural controlflow changes, including exceptions and interrupts)Retired taken branch instructions mispredictedRetired conditional branch instructionsRetired indirect branch instructionsex_ret_msprd_brnch_instr_dir_msmtchRetired branch instructions mispredicted due to direction mismatchRetired near returns (RET or RET Iw)Retired near returns mispredicted. Each misprediction incurs the samepenalty as a mispredicted conditional branch instructionRetired unconditional branch instructionsex_ret_uncond_brnch_instr_mispredRetired unconditional indirect branch instructions mispredictedInstruction cache lines (64 bytes) fulfilled from the L2 cacheInstruction cache lines (64 bytes) fulfilled from system memory oranother cacheic_tag_hit_miss.all_instruction_cache_accessesInstruction cache accesses of all typesic_tag_hit_miss.instruction_cache_hitic_tag_hit_miss.instruction_cache_missCore to L2 cache requests (not including L2 prefetch) for data andinstruction cache accessl2_cache_req_stat.dc_access_in_l2Core to L2 cache requests (not including L2 prefetch) for data cacheaccessl2_cache_req_stat.dc_hit_in_l2Core to L2 cache requests (not including L2 prefetch) for data cachehitsl2_cache_req_stat.ic_access_in_l2Core to L2 cache requests (not including L2 prefetch) for instructioncache accessl2_cache_req_stat.ic_dc_hit_in_l2Core to L2 cache requests (not including L2 prefetch) for data andinstruction cache hitsl2_cache_req_stat.ic_dc_miss_in_l2Core to L2 cache requests (not including L2 prefetch) for data andinstruction cache missesl2_cache_req_stat.ic_fill_hit_sCore to L2 cache requests (not including L2 prefetch) with status:instruction cache hit non-modifiable line in L2l2_cache_req_stat.ic_fill_hit_xCore to L2 cache requests (not including L2 prefetch) with status:instruction cache hit modifiable line in L2l2_cache_req_stat.ic_fill_missCore to L2 cache requests (not including L2 prefetch) with status:instruction cache request miss in L2l2_cache_req_stat.ic_hit_in_l2Core to L2 cache requests (not including L2 prefetch) for instructioncache hitsCore to L2 cache requests (not including L2 prefetch) with status:data cache request miss in L2l2_cache_req_stat.ls_rd_blk_csCore to L2 cache requests (not including L2 prefetch) with status:data cache shared read hit in L2l2_cache_req_stat.ls_rd_blk_l_hit_sCore to L2 cache requests (not including L2 prefetch) with status:data cache read hit non-modifiable line in L2l2_cache_req_stat.ls_rd_blk_l_hit_xCore to L2 cache requests (not including L2 prefetch) with status:data cache read hit modifiable line in L2Core to L2 cache requests (not including L2 prefetch) with status:data cache store or state change hit in L2L2 prefetches accepted by the L2 pipeline which hit in the L2 cache ofall typesL2 prefetches accepted by the L2 pipeline which hit in the L2 cache oftype L1Region (fetch additional lines into L1 cache when the dataaccess for a given instruction tends to be followed by a consistentpattern of other accesses within a localized region)L2 prefetches accepted by the L2 pipeline which hit in the L2 cache oftype L1Stream (fetch additional sequential lines into L1 cache)L2 prefetches accepted by the L2 pipeline which hit in the L2 cache oftype L1Stride (fetch additional lines into L1 cache when each accessis a constant distance from the previous)L2 prefetches accepted by the L2 pipeline which hit in the L2 cache oftype L2Burst (aggressively fetch additional sequential lines into L2cache)L2 prefetches accepted by the L2 pipeline which hit in the L2 cache oftype L2NextLine (fetch the next line into L2 cache)L2 prefetches accepted by the L2 pipeline which hit in the L2 cache oftype L2Stream (fetch additional sequential lines into L2 cache)L2 prefetches accepted by the L2 pipeline which hit in the L2 cache oftype L2Stride (fetch additional lines into L2 cache when each accessis at a constant distance from the previous)L2 prefetches accepted by the L2 pipeline which hit in the L2 cache oftype L2UpDown (fetch the next or previous line into L2 cache for allmemory accesses)L2 prefetches accepted by the L2 pipeline which miss the L2 cache andhit in the L3 cache cache of all typesl2_pf_miss_l2_hit_l3.l1_regionL2 prefetches accepted by the L2 pipeline which miss the L2 cache andhit in the L3 cache of type L1Region (fetch additional lines into L1cache when the data access for a given instruction tends to befollowed by a consistent pattern of other accesses within a localizedregion)l2_pf_miss_l2_hit_l3.l1_streamL2 prefetches accepted by the L2 pipeline which miss the L2 cache andhit in the L3 cache of type L1Stream (fetch additional sequentiallines into L1 cache)l2_pf_miss_l2_hit_l3.l1_strideL2 prefetches accepted by the L2 pipeline which miss the L2 cache andhit in the L3 cache of type L1Stride (fetch additional lines into L1cache when each access is a constant distance from the previous)L2 prefetches accepted by the L2 pipeline which miss the L2 cache andhit in the L3 cache of type L2Burst (aggressively fetch additionalsequential lines into L2 cache)l2_pf_miss_l2_hit_l3.l2_next_lineL2 prefetches accepted by the L2 pipeline which miss the L2 cache andhit in the L3 cache of type L2NextLine (fetch the next line into L2cache)l2_pf_miss_l2_hit_l3.l2_streamL2 prefetches accepted by the L2 pipeline which miss the L2 cache andhit in the L3 cache of type L2Stream (fetch additional sequentiallines into L2 cache)l2_pf_miss_l2_hit_l3.l2_strideL2 prefetches accepted by the L2 pipeline which miss the L2 cache andhit in the L3 cache of type L2Stride (fetch additional lines into L2cache when each access is a constant distance from the previous)l2_pf_miss_l2_hit_l3.l2_up_downL2 prefetches accepted by the L2 pipeline which miss the L2 cache andhit in the L3 cache of type L2UpDown (fetch the next or previous lineinto L2 cache for all memory accesses)L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3caches of all typesL2 prefetches accepted by the L2 pipeline which miss the L2 and the L3caches of type L1Region (fetch additional lines into L1 cache when thedata access for a given instruction tends to be followed by aconsistent pattern of other accesses within a localized region)L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3caches of type L1Stream (fetch additional sequential lines into L1cache)L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3caches of type L1Stride (fetch additional lines into L1 cache wheneach access is a constant distance from the previous)L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3caches of type L2Burst (aggressively fetch additional sequential linesinto L2 cache)L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3caches of type L2NextLine (fetch the next line into L2 cache)L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3caches of type L2Stream (fetch additional sequential lines into L2cache)L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3caches of type L2Stride (fetch additional lines into L2 cache wheneach access is a constant distance from the previous)L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3caches of type L2UpDown (fetch the next or previous line into L2 cachefor all memory accesses)L2 cache requests of all typesL2 cache requests of common types from L1 data cache (includingprefetches)L2 cache requests of common types not including prefetchesl2_request_g1.cacheable_ic_readL2 cache requests: instruction cache readsL2 cache requests: data cache state change to writable, check L2 forcurrent stateL2 cache requests of non-cacheable type (non-cached data andinstructions reads, self-modifying code checks)L2 cache requests: from hardware prefetchers to prefetch directly intoL2 (hit or miss)L2 cache requests: data cache shared readsL2 cache requests: prefetch directly into L2L2 cache requests: data cache reads including hardware and softwareprefetchL2 cache requests: data cache storesIn-flight L1 data cache misses i.e. Miss Address Buffer (MAB)allocations each cycleAny data cache fills from all types of data sourcesls_any_fills_from_sys.all_dram_ioAny data cache fills from either DRAM or MMIO in any NUMA node (sameor different socket)ls_any_fills_from_sys.alternate_memoriesAny data cache fills from extension memoryls_any_fills_from_sys.dram_io_allls_any_fills_from_sys.dram_io_farAny data cache fills from either DRAM or MMIO in a different NUMA node(same or different socket)ls_any_fills_from_sys.dram_io_nearAny data cache fills from either DRAM or MMIO in the same NUMA nodeAny data cache fills from either cache of another CCX, DRAM or MMIOwhen the address was in a different NUMA node (same or differentsocket)ls_any_fills_from_sys.far_cacheAny data cache fills from cache of another CCX when the address was ina different NUMA nodels_any_fills_from_sys.local_allAny data cache fills from local L2 cache or L3 cache or different L2cache in the same CCXls_any_fills_from_sys.local_ccxAny data cache fills from L3 cache or different L2 cache in the sameCCXls_any_fills_from_sys.local_l2Any data cache fills from local L2 cachels_any_fills_from_sys.near_cacheAny data cache fills from cache of another CCX when the address was inthe same NUMA nodels_any_fills_from_sys.remote_cacheAny data cache fills from cache of another CCX when the address was inthe same or a different NUMA nodeDemand data cache fills from all types of data sourcesls_dmnd_fills_from_sys.alternate_memoriesDemand data cache fills from extension memoryls_dmnd_fills_from_sys.dram_io_farDemand data cache fills from either DRAM or MMIO in a different NUMAnode (same or different socket)ls_dmnd_fills_from_sys.dram_io_nearDemand data cache fills from either DRAM or MMIO in the same NUMA nodels_dmnd_fills_from_sys.far_cacheDemand data cache fills from cache of another CCX when the address wasin a different NUMA nodels_dmnd_fills_from_sys.local_ccxDemand data cache fills from L3 cache or different L2 cache in thesame CCXls_dmnd_fills_from_sys.local_l2Demand data cache fills from local L2 cachels_dmnd_fills_from_sys.near_cacheDemand data cache fills from cache of another CCX when the address wasin the same NUMA nodeHardware prefetch data cache fills from all types of data sourcesls_hw_pf_dc_fills.alternate_memoriesHardware prefetch data cache fills from extension memoryHardware prefetch data cache fills from either DRAM or MMIO in adifferent NUMA node (same or different socket)ls_hw_pf_dc_fills.dram_io_nearHardware prefetch data cache fills from either DRAM or MMIO in thesame NUMA nodeHardware prefetch data cache fills from cache of another CCX when theaddress was in a different NUMA nodeHardware prefetch data cache fills from L3 cache or different L2 cachein the same CCXHardware prefetch data cache fills from local L2 cacheHardware prefetch data cache fills from cache of another CCX when theaddress was in the same NUMA nodels_inef_sw_pref.data_pipe_sw_pf_dc_hitSoftware prefetches that did not fetch data outside of the processorcore as the PREFETCH instruction saw a data cache hitSoftware prefetches that did not fetch data outside of the processorcore as the PREFETCH instruction saw a match on an already allocatedMiss Address Buffer (MAB)Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipefor all types of allocationsls_mab_alloc.hardware_prefetcher_allocationsMiss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipefor hardware prefetcher allocationsls_mab_alloc.load_store_allocationsMiss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipefor load-store allocationsSoftware prefetch instructions dispatched (speculative) of all typesSoftware prefetch instructions dispatched (speculative) of typePrefetchT0 (move data to all cache levels), T1 (move data to all cachelevels except L1) and T2 (move data to all cache levels except L1 andL2)ls_pref_instr_disp.prefetch_ntaSoftware prefetch instructions dispatched (speculative) of typePrefetchNTA (move data with minimum cache pollution i.e. non-temporalaccess)Software prefetch instructions dispatched (speculative) of typePrefetchW (move data to L1 cache and mark it modifiable)Software prefetch data cache fills from all types of data sourcesls_sw_pf_dc_fills.alternate_memoriesSoftware prefetch data cache fills from extension memorySoftware prefetch data cache fills from either DRAM or MMIO in adifferent NUMA node (same or different socket)ls_sw_pf_dc_fills.dram_io_nearSoftware prefetch data cache fills from either DRAM or MMIO in thesame NUMA nodeSoftware prefetch data cache fills from cache of another CCX in adifferent NUMA nodeSoftware prefetch data cache fills from L3 cache or different L2 cachein the same CCXSoftware prefetch data cache fills from local L2 cacheSoftware prefetch data cache fills from cache of another CCX in thesame NUMA nodeop_cache_hit_miss.all_op_cache_accessesOp cache accesses of all typesop_cache_hit_miss.op_cache_hitop_cache_hit_miss.op_cache_missNumber of cycles the divider is busyCycles with no retire for any reasonCycles with no retire due to the lack of valid ops in the retire queue(may be caused by front-end bottlenecks or pipeline redirects)ex_no_retire.load_not_completeCycles with no retire while the oldest op is waiting for load dataCycles with no retire while the oldest op is waiting to be executedCycles with no retire caused by other reasons (retire breaks, traps,faults, etc.)ex_no_retire.thread_not_selectedCycles with no retire because thread arbitration did not select thethreadRetired microcoded instructionsex_tagged_ibs_ops.ibs_tagged_opsex_tagged_ibs_ops.ibs_tagged_ops_retOps tagged by IBS that retiredRetired Lock instructions which caused a bus lockls_not_halted_p0_cyc.p0_freq_cycReference cycles (P0 frequency) not in haltFloating-point dispatch faults of all typesFloating-point dispatch faults of all types for SSE and AVX opsFloating-point dispatch faults for x87 fillsFloating-point dispatch faults for XMM fillsFloating-point dispatch faults for YMM fillsfp_disp_faults.ymm_spill_faultFloating-point dispatch faults for YMM spillsRetired floating-point ops of all typesfp_ops_retired_by_type.scalar_addRetired scalar floating-point add opsfp_ops_retired_by_type.scalar_allRetired scalar floating-point ops of all typesfp_ops_retired_by_type.scalar_blendRetired scalar floating-point blend opsfp_ops_retired_by_type.scalar_cmpRetired scalar floating-point compare opsfp_ops_retired_by_type.scalar_cvtRetired scalar floating-point convert opsfp_ops_retired_by_type.scalar_divRetired scalar floating-point divide opsfp_ops_retired_by_type.scalar_macRetired scalar floating-point multiply-accumulate opsfp_ops_retired_by_type.scalar_mulRetired scalar floating-point multiply opsfp_ops_retired_by_type.scalar_otherRetired scalar floating-point ops of other typesfp_ops_retired_by_type.scalar_sqrtRetired scalar floating-point square root opsfp_ops_retired_by_type.scalar_subRetired scalar floating-point subtract opsfp_ops_retired_by_type.vector_addRetired vector floating-point add opsfp_ops_retired_by_type.vector_allRetired vector floating-point ops of all typesfp_ops_retired_by_type.vector_blendRetired vector floating-point blend opsfp_ops_retired_by_type.vector_cmpRetired vector floating-point compare opsfp_ops_retired_by_type.vector_cvtRetired vector floating-point convert opsfp_ops_retired_by_type.vector_divRetired vector floating-point divide opsfp_ops_retired_by_type.vector_logicalRetired vector floating-point logical opsfp_ops_retired_by_type.vector_macRetired vector floating-point multiply-accumulate opsfp_ops_retired_by_type.vector_mulRetired vector floating-point multiply opsfp_ops_retired_by_type.vector_otherRetired vector floating-point ops of other typesfp_ops_retired_by_type.vector_shuffleRetired vector floating-point shuffle ops (may include instructionsnot necessarily thought of as including shuffles e.g. horizontal add,dot product, and certain MOV instructions)fp_ops_retired_by_type.vector_sqrtRetired vector floating-point square root opsfp_ops_retired_by_type.vector_subRetired vector floating-point subtract opsRetired floating-point ops of all widthsfp_ops_retired_by_width.mmx_uops_retiredRetired MMX floating-point opsfp_ops_retired_by_width.pack_128_uops_retiredRetired packed 128-bit floating-point opsfp_ops_retired_by_width.pack_256_uops_retiredRetired packed 256-bit floating-point opsfp_ops_retired_by_width.pack_512_uops_retiredRetired packed 512-bit floating-point opsfp_ops_retired_by_width.scalar_uops_retiredRetired scalar floating-point opsfp_ops_retired_by_width.x87_uops_retiredRetired x87 floating-point opsRetired packed floating-point ops of all typesRetired 128-bit packed floating-point add opsRetired 128-bit packed floating-point ops of all typesfp_pack_ops_retired.fp128_blendRetired 128-bit packed floating-point blend opsRetired 128-bit packed floating-point compare opsRetired 128-bit packed floating-point convert opsRetired 128-bit packed floating-point divide opsfp_pack_ops_retired.fp128_logicalRetired 128-bit packed floating-point logical opsRetired 128-bit packed floating-point multiply-accumulate opsRetired 128-bit packed floating-point multiply opsfp_pack_ops_retired.fp128_otherRetired 128-bit packed floating-point ops of other typesfp_pack_ops_retired.fp128_shuffleRetired 128-bit packed floating-point shuffle ops (may includeinstructions not necessarily thought of as including shuffles e.g.horizontal add, dot product, and certain MOV instructions)fp_pack_ops_retired.fp128_sqrtRetired 128-bit packed floating-point square root opsRetired 128-bit packed floating-point subtract opsRetired 256-bit packed floating-point add opsRetired 256-bit packed floating-point ops of all typesfp_pack_ops_retired.fp256_blendRetired 256-bit packed floating-point blend opsRetired 256-bit packed floating-point compare opsRetired 256-bit packed floating-point convert opsRetired 256-bit packed floating-point divide opsfp_pack_ops_retired.fp256_logicalRetired 256-bit packed floating-point logical opsRetired 256-bit packed floating-point multiply-accumulate opsRetired 256-bit packed floating-point multiply opsfp_pack_ops_retired.fp256_otherRetired 256-bit packed floating-point ops of other typesfp_pack_ops_retired.fp256_shuffleRetired 256-bit packed floating-point shuffle ops (may includeinstructions not necessarily thought of as including shuffles e.g.horizontal add, dot product, and certain MOV instructions)fp_pack_ops_retired.fp256_sqrtRetired 256-bit packed floating-point square root opsRetired 256-bit packed floating-point subtract opsfp_ret_sse_avx_ops.add_sub_flopsRetired SSE and AVX floating-point add and subtract opsRetired SSE and AVX floating-point ops of all typesfp_ret_sse_avx_ops.bfloat_mac_flopsRetired SSE and AVX floating-point bfloat multiply-accumulate ops(each operation is counted as 2 ops)Retired SSE and AVX floating-point divide and square root opsRetired SSE and AVX floating-point multiply-accumulate ops (eachoperation is counted as 2 ops)Retired SSE and AVX floating-point multiply opsRetired x87 floating-point add and subtract opsRetired x87 floating-point ops of all typesfp_ret_x87_fp_ops.div_sqrt_opsRetired x87 floating-point divide and square root opsRetired x87 floating-point multiply opsRetired SSE and AVX serializing ops of all typesfp_retired_ser_ops.sse_bot_retRetired SSE and AVX bottom-executing ops. Bottom-executing ops waitfor all older ops to retire before executingfp_retired_ser_ops.sse_ctrl_retRetired SSE and AVX control word mispredict trapsfp_retired_ser_ops.x87_bot_retRetired x87 bottom-executing ops. Bottom-executing ops wait for allolder ops to retire before executingfp_retired_ser_ops.x87_ctrl_retRetired x87 control word mispredict traps due to mispredictions in RCor PC, or changes in exception mask bitsRetired packed integer ops of all typesRetired 128-bit packed integer add opsRetired 128-bit packed integer AES opsRetired 128-bit packed integer ops of all typesRetired 128-bit packed integer CLM opsRetired 128-bit packed integer compare opspacked_int_op_type.int128_logicalRetired 128-bit packed integer logical opsRetired 128-bit packed integer multiply-accumulate opsRetired 128-bit packed integer MOV opsRetired 128-bit packed integer multiply opspacked_int_op_type.int128_otherRetired 128-bit packed integer ops of other typespacked_int_op_type.int128_packRetired 128-bit packed integer pack opsRetired 128-bit packed integer SHA opspacked_int_op_type.int128_shiftRetired 128-bit packed integer shift opspacked_int_op_type.int128_shuffleRetired 128-bit packed integer shuffle ops (may include instructionsnot necessarily thought of as including shuffles e.g. horizontal add,dot product, and certain MOV instructions)Retired 128-bit packed integer subtract opsRetired 256-bit packed integer add opsRetired 256-bit packed integer ops of all typesRetired 256-bit packed integer compare opspacked_int_op_type.int256_logicalRetired 256-bit packed integer logical opsRetired 256-bit packed integer multiply-accumulate opsRetired 256-bit packed integer MOV opsRetired 256-bit packed integer multiply opspacked_int_op_type.int256_otherRetired 256-bit packed integer ops of other typespacked_int_op_type.int256_packRetired 256-bit packed integer pack opspacked_int_op_type.int256_shiftRetired 256-bit packed integer shift opspacked_int_op_type.int256_shuffleRetired 256-bit packed integer shuffle ops (may include instructionsnot necessarily thought of as including shuffles e.g. horizontal add,dot product, and certain MOV instructions)Retired 256-bit packed integer subtract opsRetired SSE, AVX and MMX integer ops of all typesRetired MMX integer ops of all typesRetired MMX integer compare opssse_avx_ops_retired.mmx_logicalRetired MMX integer logical opsRetired MMX integer multiply-accumulate opsRetired MMX integer multiply opsRetired MMX integer multiply ops of other typessse_avx_ops_retired.mmx_shuffleRetired MMX integer shuffle ops (may include instructions notnecessarily thought of as including shuffles e.g. horizontal add, dotproduct, and certain MOV instructions)Retired MMX integer subtract opssse_avx_ops_retired.sse_avx_addRetired SSE and AVX integer add opssse_avx_ops_retired.sse_avx_aesRetired SSE and AVX integer AES opssse_avx_ops_retired.sse_avx_allRetired SSE and AVX integer ops of all typessse_avx_ops_retired.sse_avx_clmRetired SSE and AVX integer CLM opssse_avx_ops_retired.sse_avx_cmpRetired SSE and AVX integer compare opssse_avx_ops_retired.sse_avx_logicalRetired SSE and AVX integer logical opssse_avx_ops_retired.sse_avx_macRetired SSE and AVX integer multiply-accumulate opssse_avx_ops_retired.sse_avx_movRetired SSE and AVX integer MOV opssse_avx_ops_retired.sse_avx_mulRetired SSE and AVX integer multiply opssse_avx_ops_retired.sse_avx_otherRetired SSE and AVX integer ops of other typessse_avx_ops_retired.sse_avx_packRetired SSE and AVX integer pack opssse_avx_ops_retired.sse_avx_shaRetired SSE and AVX integer SHA opssse_avx_ops_retired.sse_avx_shiftRetired SSE and AVX integer shift opssse_avx_ops_retired.sse_avx_shuffleRetired SSE and AVX integer shuffle ops (may include instructions notnecessarily thought of as including shuffles e.g. horizontal add, dotproduct, and certain MOV instructions)sse_avx_ops_retired.sse_avx_subRetired SSE and AVX integer subtract opsInstruction fetches that hit in the L1 ITLB for all page sizesInstruction fetches that hit in the L1 ITLB for 1G pagesInstruction fetches that hit in the L1 ITLB for 2M pagesInstruction fetches that hit in the L1 ITLB for 4k or coalesced pages.A coalesced page is a 16k page created from four adjacent 4k pagesInstruction fetches that miss in the L1 ITLB but hit in the L2 ITLBbp_l1_tlb_miss_l2_tlb_miss.allInstruction fetches that miss in both the L1 and L2 ITLBs (page-tablewalks are requested) for all page sizesbp_l1_tlb_miss_l2_tlb_miss.coalesced_4kInstruction fetches that miss in both the L1 and L2 ITLBs (page-tablewalks are requested) for coalesced pages. A coalesced page is a 16kpage created from four adjacent 4k pagesbp_l1_tlb_miss_l2_tlb_miss.if1gInstruction fetches that miss in both the L1 and L2 ITLBs (page-tablewalks are requested) for 1G pagesbp_l1_tlb_miss_l2_tlb_miss.if2mInstruction fetches that miss in both the L1 and L2 ITLBs (page-tablewalks are requested) for 2M pagesbp_l1_tlb_miss_l2_tlb_miss.if4kInstruction fetches that miss in both the L1 and L2 ITLBs (page-tablewalks are requested) for 4k pagesStore-to-load conflicts (load unable to complete due to anon-forwardable conflict with an older store)Number of memory load operations dispatched to the load-store unitNumber of memory load-store operations dispatched to the load-storeunitNumber of memory store operations dispatched to the load-store unitL1 DTLB misses for all page sizesL1 DTLB misses with L2 DTLB misses (page-table walks are requested)for all page sizesls_l1_d_tlb_miss.tlb_reload_1g_l2_hitL1 DTLB misses with L2 DTLB hits for 1G pagesls_l1_d_tlb_miss.tlb_reload_1g_l2_missL1 DTLB misses with L2 DTLB misses (page-table walks are requested)for 1G pagesls_l1_d_tlb_miss.tlb_reload_2m_l2_hitL1 DTLB misses with L2 DTLB hits for 2M pagesls_l1_d_tlb_miss.tlb_reload_2m_l2_missL1 DTLB misses with L2 DTLB misses (page-table walks are requested)for 2M pagesls_l1_d_tlb_miss.tlb_reload_4k_l2_hitL1 DTLB misses with L2 DTLB hits for 4k pagesls_l1_d_tlb_miss.tlb_reload_4k_l2_missL1 DTLB misses with L2 DTLB misses (page-table walks are requested)for 4k pagesls_l1_d_tlb_miss.tlb_reload_coalesced_page_hitL1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced pageis a 16k page created from four adjacent 4k pagesls_l1_d_tlb_miss.tlb_reload_coalesced_page_missL1 DTLB misses with L2 DTLB misses (page-table walks are requested)for coalesced pages. A coalesced page is a 16k page created from fouradjacent 4k pages4kB misaligned (page crossing) loads64B misaligned (cacheline crossing) loadsls_st_commit_cancel2.st_commit_cancel_wcb_fullNon-cacheable store commits cancelled due to the non-cacheable commitbuffer being fullStore-to-load-forward (STLF) hitsde_dis_dispatch_token_stalls1.fp_flush_recovery_stallNumber of cycles dispatch is stalled for floating-point flush recoveryde_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stallNumber of cycles dispatch is stalled for floating-point register filetokensde_dis_dispatch_token_stalls1.fp_sch_rsrc_stallNumber of cycles dispatch is stalled for floating-point schedulertokensde_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stallNumber of cycles dispatch is stalled for integer physical registerfile tokensde_dis_dispatch_token_stalls1.load_queue_rsrc_stallNumber of cycles dispatch is stalled for Load queue tokende_dis_dispatch_token_stalls1.store_queue_rsrc_stallNumber of cycles dispatch is stalled for store queue tokensde_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrcNumber of cycles dispatch is stalled for taken branch buffer tokensde_dis_dispatch_token_stalls2.int_sch0_token_stallNumber of cycles dispatch is stalled for integer scheduler queue 0tokensde_dis_dispatch_token_stalls2.int_sch1_token_stallNumber of cycles dispatch is stalled for integer scheduler queue 1tokensde_dis_dispatch_token_stalls2.int_sch2_token_stallNumber of cycles dispatch is stalled for integer scheduler queue 2tokensde_dis_dispatch_token_stalls2.int_sch3_token_stallNumber of cycles dispatch is stalled for integer scheduler queue 3tokensde_dis_dispatch_token_stalls2.retire_token_stallNumber of cycles dispatch is stalled for retire queue tokensde_dis_ops_from_decoder.any_fp_dispatchNumber of ops dispatched to the floating-point unitde_dis_ops_from_decoder.disp_op_type.any_integer_dispatchNumber of ops dispatched to the integer execution unitde_no_dispatch_per_slot.backend_stallsIn each cycle counts ops unable to dispatch because of back-end stallsde_no_dispatch_per_slot.no_ops_from_frontendIn each cycle counts dispatch slots left empty because the front-enddid not supply opsde_no_dispatch_per_slot.smt_contentionIn each cycle counts ops unable to dispatch because the dispatch cyclewas granted to the other SMT threadCycles when the op queue is empty. Such cycles indicate that thefront-end is not delivering instructions fast enoughOps dispatched from any sourceOps fetched from instruction cache and dispatchedOps dispatched from loop bufferOps fetched from op cache and dispatchedPipeline restarts not caused by branch mispredictsL1 Branch Prediction Overrides Existing Prediction (speculative)The number of instruction fetches that hit in the L1 ITLBThe number of instruction fetches that hit in the L1 ITLB. L1Instruction TLB hit (1G page size)The number of instruction fetches that hit in the L1 ITLB. L1Instruction TLB hit (2M page size)The number of instruction fetches that hit in the L1 ITLB. L1Instrcution TLB hit (4K or 16K page size)L2 Branch Prediction Overrides Existing Prediction (speculative)The number of ITLB reload requestsL1 ITLB Miss, L2 ITLB Hit. The number of instruction fetches that missin the L1 ITLB but hit in the L2 ITLBThe number of instruction fetches that miss in both the L1 and L2 TLBsThe number of valid fills into the ITLB originating from the LSPage-Table Walker. Tablewalk requests are issued for L1-ITLB andL2-ITLB misses. Walk for >4K Coalesced pageThe number of valid fills into the ITLB originating from the LSPage-Table Walker. Tablewalk requests are issued for L1-ITLB andL2-ITLB misses. Walk for 1G pageThe number of valid fills into the ITLB originating from the LSPage-Table Walker. Tablewalk requests are issued for L1-ITLB andL2-ITLB misses. Walk for 2M pageThe number of valid fills into the ITLB originating from the LSPage-Table Walker. Tablewalk requests are issued for L1-ITLB andL2-ITLB misses. Walk to 4K pageThe number of pipeline restarts caused by invalidating probes that hiton the instruction stream currently being executed. This would happenif the active instruction stream was being modified by anotherprocessor in an MP system - typically a highly unlikely eventInstruction Cache Refills from L2. The number of 64 byte instructioncache line was fulfilled from the L2 cacheInstruction Cache Refills from System. The number of 64 byteinstruction cache line fulfilled from system memory or another cacheic_cache_inval.fill_invalidatedIC line invalidated due to overwriting fill response. The number ofinstruction cache lines invalidated. A non-SMC event is CMC (crossmodifying code), either from the other thread of the core or anothercoreic_cache_inval.l2_invalidating_probeIC line invalidated due to L2 invalidating probe (external or LS). Thenumber of instruction cache lines invalidated. A non-SMC event is CMC(cross modifying code), either from the other thread of the core oranother coreInstruction Pipe Stall. IC pipe was stalled during this clock cyclefor any reason (nothing valid in pipe ICM1)ic_fetch_stall.ic_stall_back_pressureInstruction Pipe Stall. IC pipe was stalled during this clock cycle(including IC to OC fetches) due to back-pressureic_fetch_stall.ic_stall_dq_emptyInstruction Pipe Stall. IC pipe was stalled during this clock cycle(including IC to OC fetches) due to DQ emptyThe number of 32B fetch windows transferred from IC pipe to DEinstruction decoder (includes non-cacheable and cacheable fillresponses)The number of 32B fetch windows tried to read the L1 IC and missed inthe full tagic_oc_mode_switch.ic_oc_mode_switchOC Mode Switch. IC to OC mode switchic_oc_mode_switch.oc_ic_mode_switchOC Mode Switch. OC to IC mode switchAll Instruction Cache Accesses. Counts various IC tag related hit andmiss eventsInstruction Cache Hit. Counts various IC tag related hit and misseventsInstruction Cache Miss. Counts various IC tag related hit and misseventsCore to L2 cacheable request access status (not including L2Prefetch). Instruction cache requests in L2Core to L2 cacheable request access status (not including L2Prefetch). Instruction cache request hit in L2 and Data cache requesthit in L2 (all types)Core to L2 cacheable request access status (not including L2Prefetch). Instruction cache request miss in L2 and Data cache requestmiss in L2 (all types)Core to L2 cacheable request access status (not including L2Prefetch). Instruction cache hit non-modifiable line in L2Core to L2 cacheable request access status (not including L2Prefetch). Instruction cache hit modifiable line in L2Core to L2 cacheable request access status (not including L2Prefetch). Instruction cache request miss in L2. Usel2_cache_misses_from_ic_miss insteadCore to L2 cacheable request access status (not including L2Prefetch). Data cache request miss in L2 (all types). Usel2_cache_misses_from_dc_misses insteadCore to L2 cacheable request access status (not including L2Prefetch). Data cache shared read hit in L2Core to L2 cacheable request access status (not including L2Prefetch). Data cache read hit non-modifiable line in L2Core to L2 cacheable request access status (not including L2Prefetch). Data cache read hit in L2. ModifiableCore to L2 cacheable request access status (not including L2Prefetch). Data cache store or state change hit in L2Cycles with fill pending from L2. Total cycles spent with one or morefill requests in flight from L2l2_latency.l2_cycles_waiting_on_fillsTotal cycles spent waiting for L2 fills to complete from L3 or memory,divided by four. Event counts are for both threads. To calculateaverage latency, the number of fills from both threads must be usedL2 prefetch hit in L2. Use l2_cache_hits_from_l2_hwpf insteadL2 prefetcher hits in L3. Counts all L2 prefetches accepted by the L2pipeline which miss the L2 cache and hit the L3L2 prefetcher misses in L3. Counts all L2 prefetches accepted by theL2 pipeline which miss the L2 and the L3 cachesAll L2 Cache Requests (Breakdown 1 - Common). Instruction cache readsAll L2 Cache Requests (Breakdown 1 - Common). Data cache state changerequests. Request change to writable, check L2 for current stateMiscellaneous events covered in more detail by l2_request_g2 (PMCx061)All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. Allprefetches accepted by L2 pipeline, hit or miss. Types of PF and L2hit/miss broken out in a separate perfmon eventAll L2 Cache Requests (Breakdown 1 - Common). Data cache shared readsAll L2 Cache Requests (Breakdown 1 - Common). PrefetchL2CmdAll L2 Cache Requests (Breakdown 1 - Common). Data cache reads(including hardware and software prefetch)All L2 Cache Requests (Breakdown 1 - Common). Data cache storesl2_request_g2.bus_locks_originatorAll L2 Cache Requests (Breakdown 2 - Rare). Bus locksl2_request_g2.bus_locks_responsesAll L2 Cache Requests (Breakdown 2 - Rare). Bus lock responseMiscellaneous events covered in more detail by l2_request_g1 (PMCx060)All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache readsizedAll L2 Cache Requests (Breakdown 2 - Rare). Instruction cache readsized non-cacheableAll L2 Cache Requests (Breakdown 2 - Rare). Data cache read sizedAll L2 Cache Requests (Breakdown 2 - Rare). Data cache read sizednon-cacheableAll L2 Cache Requests (Breakdown 2 - Rare). Self-modifying codeinvalidatesLS to L2 WCB cache line zeroing requests. LS (Load/Store unit) to L2WCB (Write Combining Buffer) cache line zeroing requestsLS to L2 WCB close requests. LS (Load/Store unit) to L2 WCB (WriteCombining Buffer) close requestsLS to L2 WCB write requests. LS (Load/Store unit) to L2 WCB (WriteCombining Buffer) write requestsLS to L2 WCB zero byte store requests. LS (Load/Store unit) to L2 WCB(Write Combining Buffer) zero byte store requestsAll Op Cache accesses. Counts Op Cache micro-tag hit/miss eventsOp Cache Hit. Counts Op Cache micro-tag hit/miss eventsOp Cache Miss. Counts Op Cache micro-tag hit/miss eventsRetired Indirect Branch Instructions MispredictedRetired Branch Instructions MispredictedRetired Taken Branch InstructionsRetired Taken Branch Instructions MispredictedRetired Conditional Branch InstructionsCounts retired Fused InstructionsRetired Indirect Branch Instructions. The number of indirect branchesretiredSSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX)Retired Mispredicted Branch Instructions due to Direction MismatchRetired Near Returns MispredictedRetired Ops. Use macro_ops_retired insteadex_tagged_ibs_ops.ibs_count_rolloverTagged IBS Ops. Number of times an op could not be tagged by IBSbecause of a previous tagged op that has not retiredTagged IBS Ops. Number of Ops tagged by IBSTagged IBS Ops. Number of Ops tagged by IBS that retiredFloating Point Dispatch Faults. x87 fill faultFloating Point Dispatch Faults. XMM fill faultFloating Point Dispatch Faults. YMM fill faultFloating Point Dispatch Faults. YMM spill faultfp_num_mov_elim_scal_op.opt_potentialNumber of Ops that are candidates for optimization (have Z-bit eitherset or pass). This is a dispatch based speculative event, and isuseful for measuring the effectiveness of the Move elimination andScalar code optimization schemesfp_num_mov_elim_scal_op.optimizedNumber of Scalar Ops optimized. This is a dispatch based speculativeevent, and is useful for measuring the effectiveness of the Moveelimination and Scalar code optimization schemesfp_num_mov_elim_scal_op.sse_mov_opsNumber of SSE Move Ops. This is a dispatch based speculative event,and is useful for measuring the effectiveness of the Move eliminationand Scalar code optimization schemesfp_num_mov_elim_scal_op.sse_mov_ops_elimNumber of SSE Move Ops eliminated. This is a dispatch basedspeculative event, and is useful for measuring the effectiveness ofthe Move elimination and Scalar code optimization schemesAdd/subtract FLOPs. This is a retire-based event. The number ofretired SSE/AVX FLOPs. The number of events logged per cycle can varyfrom 0 to 64. This event requires the use of the MergeEvent since itcan count above 15 events per cycle. See 2.1.17.3 [Large Increment perCycle Events]. It does not provide a useful count without the use ofthe MergeEventAll FLOPS. This is a retire-based event. The number of retired SSE/AVXFLOPS. The number of events logged per cycle can vary from 0 to 64.This event can count above 15Divide/square root FLOPs. This is a retire-based event. The number ofretired SSE/AVX FLOPs. The number of events logged per cycle can varyfrom 0 to 64. This event requires the use of the MergeEvent since itcan count above 15 events per cycle. See 2.1.17.3 [Large Increment perCycle Events]. It does not provide a useful count without the use ofthe MergeEventMultiply-Accumulate FLOPs. Each MAC operation is counted as 2 FLOPS.This is a retire-based event. The number of retired SSE/AVX FLOPs. Thenumber of events logged per cycle can vary from 0 to 64. This eventrequires the use of the MergeEvent since it can count above 15 eventsper cycle. See 2.1.17.3 [Large Increment per Cycle Events]. It doesnot provide a useful count without the use of the MergeEventMultiply FLOPs. This is a retire-based event. The number of retiredSSE/AVX FLOPs. The number of events logged per cycle can vary from 0to 64. This event requires the use of the MergeEvent since it cancount above 15 events per cycle. See 2.1.17.3 [Large Increment perCycle Events]. It does not provide a useful count without the use ofthe MergeEventSSE/AVX bottom-executing ops retired. The number of serializing OpsretiredSSE/AVX control word mispredict traps. The number of serializing Opsretiredx87 bottom-executing ops retired. The number of serializing Opsretiredx87 control word mispredict traps due to mispredictions in RC or PC,or changes in mask bits. The number of serializing Ops retiredTotal number of fp uOps on pipe 0Total number uOps assigned to pipe 1Total number uOps assigned to pipe 2Total number uOps assigned to pipe 3ls_any_fills_from_sys.ext_cache_localAny Data Cache Fills by Data Source. From cache of different CCX insame nodels_any_fills_from_sys.ext_cache_remoteAny Data Cache Fills by Data Source. From CCX Cache in different Nodels_any_fills_from_sys.int_cacheAny Data Cache Fills by Data Source. From L3 or different L2 in sameCCXAny Data Cache Fills by Data Source. From Local L2 to the corels_any_fills_from_sys.mem_io_localAny Data Cache Fills by Data Source. From DRAM or IO connected in samenodels_any_fills_from_sys.mem_io_remoteAny Data Cache Fills by Data Source. From DRAM or IO connected indifferent NodeNon-forwardable conflict; used to reduce STLI's via software. Allreasons. Store To Load Interlock (STLI) are loads that were unable tocomplete because of a possible match with an older store, and theolder store could not do STLF for some reasonNumber of accesses to the dcache for load/store referencesDispatch of a single op that performs a memory load. Counts the numberof operations dispatched to the LS unit. Unit Masks ADDedLoad-op-Store Dispatch. Dispatch of a single op that performs a loadfrom and store to the same memory address. Counts the number ofoperations dispatched to the LS unit. Unit Masks ADDedDispatch of a single op that performs a memory store. Counts thenumber of operations dispatched to the LS unit. Unit Masks ADDedls_dmnd_fills_from_sys.ext_cache_localDemand Data Cache Fills by Data Source. From cache of different CCX insame nodels_dmnd_fills_from_sys.ext_cache_remoteDemand Data Cache Fills by Data Source. From CCX Cache in differentNodels_dmnd_fills_from_sys.int_cacheDemand Data Cache Fills by Data Source. From L3 or different L2 insame CCXDemand Data Cache Fills by Data Source. From Local L2 to the corels_dmnd_fills_from_sys.mem_io_localDemand Data Cache Fills by Data Source. From DRAM or IO connected insame nodels_dmnd_fills_from_sys.mem_io_remoteDemand Data Cache Fills by Data Source. From DRAM or IO connected indifferent Nodels_hw_pf_dc_fills.ext_cache_localHardware Prefetch Data Cache Fills by Data Source. From cache ofdifferent CCX in same nodels_hw_pf_dc_fills.ext_cache_remoteHardware Prefetch Data Cache Fills by Data Source. From CCX Cache indifferent NodeHardware Prefetch Data Cache Fills by Data Source. From L3 ordifferent L2 in same CCXHardware Prefetch Data Cache Fills by Data Source. From Local L2 tothe corels_hw_pf_dc_fills.mem_io_localHardware Prefetch Data Cache Fills by Data Source. From DRAM or IOconnected in same nodels_hw_pf_dc_fills.mem_io_remoteHardware Prefetch Data Cache Fills by Data Source. From DRAM or IOconnected in different NodeThe number of software prefetches that did not fetch data outside ofthe processor core. Software PREFETCH instruction saw a DC hitThe number of software prefetches that did not fetch data outside ofthe processor core. Software PREFETCH instruction saw a match on analready-allocated miss request bufferCounts the number of interrupts takenAll L1 DTLB Misses or Reloads. Use l1_dtlb_misses insteadL1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLBL1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLBL1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLBL1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLBL1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLBL1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLBL1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLBL1 DTLB Miss. DTLB reload coalesced page that also missed in the L2TLBRetired lock instructions. Comparable to legacy bus lockRetired lock instructions. Non-speculative lock succeededRetired lock instructions. High speculative cacheable lock speculationsucceededRetired lock instructions. Low speculative cacheable lock speculationsucceededAll Allocations. Counts when a LS pipe allocates a MAB entryLS MAB Allocates by Type. DC prefetcherHardware Prefetcher Allocations. Counts when a LS pipe allocates a MABentryLoad Store Allocations. Counts when a LS pipe allocates a MAB entryLS MAB Allocates by Type. LoadsLS MAB Allocates by Type. StoresThe number of 4KB misaligned (i.e., page crossing) loadsThe number of 64B misaligned (i.e., cacheline crossing) loadsSoftware Prefetch Instructions Dispatched (Speculative)Software Prefetch Instructions Dispatched (Speculative). PrefetchT0,T1 and T2 instructions. See docAPM3 PREFETCHlevelSoftware Prefetch Instructions Dispatched (Speculative). PrefetchNTAinstruction. See docAPM3 PREFETCHlevelSoftware Prefetch Instructions Dispatched (Speculative). PrefetchWinstruction. See docAPM3 PREFETCHWNumber of reads of the TSC (RDTSC instructions). The count isspeculativeThe number of retired CLFLUSH instructions. This is a non-speculativeeventThe number of CPUID instructions retiredCounts the number of SMIs receivedA non-cacheable store and the non-cacheable commit buffer is fullls_sw_pf_dc_fills.ext_cache_localSoftware Prefetch Data Cache Fills by Data Source. From cache ofdifferent CCX in same nodels_sw_pf_dc_fills.ext_cache_remoteSoftware Prefetch Data Cache Fills by Data Source. From CCX Cache indifferent NodeSoftware Prefetch Data Cache Fills by Data Source. From L3 ordifferent L2 in same CCXSoftware Prefetch Data Cache Fills by Data Source. From Local L2 tothe corels_sw_pf_dc_fills.mem_io_localSoftware Prefetch Data Cache Fills by Data Source. From DRAM or IOconnected in same nodels_sw_pf_dc_fills.mem_io_remoteSoftware Prefetch Data Cache Fills by Data Source. From DRAM or IOconnected in different NodeTotal Page Table Walks DC Type 0Total Page Table Walks DC Type 1Total Page Table Walks on D-sideTotal Page Table Walks IC Type 0Total Page Table Walks IC Type 1Total Page Table Walks on I-sideAll TLB Flushes. Requires unit mask 0xFF to engage event for counting.Use all_tlbs_flushed insteadde_dis_cops_from_decoder.disp_op_type.any_fp_dispatchAny FP dispatch. Types of Oops Dispatched from Decoderde_dis_cops_from_decoder.disp_op_type.any_integer_dispatchAny Integer dispatch. Types of Oops Dispatched from DecoderCycles where a dispatch group is valid but does not get dispatched dueto a Token Stall. Also counts cycles when the thread is not selectedto dispatch but would have been stalled due to a Token Stall. FP Flushrecovery stallCycles where a dispatch group is valid but does not get dispatched dueto a Token Stall. Also counts cycles when the thread is not selectedto dispatch but would have been stalled due to a Token Stall. Floatingpoint register file resource stall. Applies to all FP ops that have adestination registerCycles where a dispatch group is valid but does not get dispatched dueto a Token Stall. Also counts cycles when the thread is not selectedto dispatch but would have been stalled due to a Token Stall. FPscheduler resource stall. Applies to ops that use the FP schedulerCycles where a dispatch group is valid but does not get dispatched dueto a Token Stall. Also counts cycles when the thread is not selectedto dispatch but would have been stalled due to a Token Stall. IntegerPhysical Register File resource stall. Integer Physical Register File,applies to all ops that have an integer destination registerde_dis_dispatch_token_stalls1.int_sched_misc_token_stallCycles where a dispatch group is valid but does not get dispatched dueto a token stall. Integer Scheduler miscellaneous resource stallCycles where a dispatch group is valid but does not get dispatched dueto a Token Stall. Also counts cycles when the thread is not selectedto dispatch but would have been stalled due to a Token Stall. LoadQueue resource stall. Applies to all ops with load semanticsCycles where a dispatch group is valid but does not get dispatched dueto a Token Stall. Also counts cycles when the thread is not selectedto dispatch but would have been stalled due to a Token Stall. StoreQueue resource stall. Applies to all ops with store semanticsCycles where a dispatch group is valid but does not get dispatched dueto a Token Stall. Also counts cycles when the thread is not selectedto dispatch but would have been stalled due to a Token Stall. Takenbranch buffer resource stallde_dis_dispatch_token_stalls2.agsq_token_stallCycles where a dispatch group is valid but does not get dispatched dueto a token stall. AGSQ Tokens unavailableCycles where a dispatch group is valid but does not get dispatched dueto a token stall. No tokens for Integer Scheduler Queue 0 availableCycles where a dispatch group is valid but does not get dispatched dueto a token stall. No tokens for Integer Scheduler Queue 1 availableCycles where a dispatch group is valid but does not get dispatched dueto a token stall. No tokens for Integer Scheduler Queue 2 availableCycles where a dispatch group is valid but does not get dispatched dueto a token stall. No tokens for Integer Scheduler Queue 3 availableCycles where a dispatch group is valid but does not get dispatched dueto a token stall. Insufficient Retire Queue tokens availableCycles where the Micro-Op Queue is emptyl1_data_cache_fills_from_external_ccx_cacheL1 Data Cache Fills: From External CCX Cachel1_data_cache_fills_from_memoryL1 Data Cache Fills: From Memoryl1_data_cache_fills_from_remote_nodeL1 Data Cache Fills: From Remote Nodel1_data_cache_fills_from_within_same_ccxL1 Data Cache Fills: From within same CCXl2_cache_accesses_from_dc_missesL2 Cache Accesses from L1 Data Cache Misses (including prefetch)l2_cache_accesses_from_ic_missesL2 Cache Accesses from L1 Instruction Cache Misses (includingprefetch)L2 Cache Hits from L1 Data Cache MissesL2 Cache Hits from L1 Instruction Cache MissesL2 Cache Hits from L2 Cache HWPFl2_cache_misses_from_dc_missesL2 Cache Misses from L1 Data Cache MissesL2 Cache Misses from L1 Instruction Cache MissesL2 DTLB Misses & Data page walksL2 ITLB Misses & Instruction page walksEX_intr_masked_while_pending_cyclesDE_dispatch_stall_serializationDE_dispatch_stall_instr_retire_q_fullDE_dispatch_stall_int_scheduler_q_fullDE_dispatch_stall_fp_scheduler_q_fullDE_dispatch_stall_waiting_all_quietFR_retired_x86_instr_w_excp_intrBU_fill_req_missed_L2~umask=0x1BU_fill_req_missed_L2~umask=0x2FP_dispatched_fpu_ops~umask=0x1FP_dispatched_fpu_ops~umask=0x2FR_dispatch_stall_branch_abort_to_retireFR_dispatch_stall_far_ctl_trsfr_resync_branch_pendFR_dispatch_stall_reorder_buffer_fullFR_dispatch_stall_resv_stations_fullFR_dispatch_stall_segment_loadFR_dispatch_stall_serializationFR_dispatch_stall_waiting_all_quietFR_intr_masked_while_pending_cyclesNB_mem_ctrlr_dram_cmd_slots_missedcycles_int_masked.cycles_int_maskedcycles_int_masked.cycles_int_pending_and_maskedPERF_COUNT_HW_CACHE_MISSES.L1DPERF_COUNT_HW_BRANCH_INSTRUCTIONSCounts the number of cache lines replaced in L1 data cacheNumber of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailabilityNumber of phases a demand request has waited due to L1D Fill Buffer (FB) unavailabilityNumber of cycles a demand request has waited due to L1D due to lack of L2 resourcesNumber of L1D misses that are outstandingCycles with L1D load Misses outstandingCache lines that are evicted by L2 cache when triggered by an L2 cache fillNon-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fillDemand requests that miss L2 cacheL2 cache hits when fetching instructions, code readsL2 cache misses when fetching instructionsDemand Data Read requests that hit L2 cacheDemand Data Read miss L2, no rejectsRFO requests that hit L2 cacheRFO requests that miss L2 cacheSW prefetch requests that hit L2 cacheSW prefetch requests that miss L2 cacheL2 writebacks that access L2 cacheCore-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)Retired load instructions Supports address when precise (Precise event)Retired store instructions Supports address when precise (Precise event)All retired memory instructions Supports address when precise (Precise event)Retired load instructions with locked access Supports address when precise (Precise event)Retired load instructions that split across a cacheline boundary Supports address when precise (Precise event)Retired store instructions that split across a cacheline boundary Supports address when precise (Precise event)mem_inst_retired.stlb_miss_loadsRetired load instructions that miss the STLB Supports address when precise (Precise event)mem_inst_retired.stlb_miss_storesRetired store instructions that miss the STLB Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_fwdRetired load instructions whose data sources were HitM responses from shared L3 Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_missRetired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_no_fwdRetired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache Supports address when precise (Precise event)mem_load_l3_hit_retired.xsnp_noneRetired load instructions whose data sources were hits in L3 without snoops required Supports address when precise (Precise event)mem_load_l3_miss_retired.local_dramRetired load instructions which data sources missed L3 but serviced from local dram Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_dramRetired load instructions which data sources missed L3 but serviced from remote dram Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_fwdRetired load instructions whose data sources was forwarded from a remote cache Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_hitmRetired load instructions whose data sources was remote HITM Supports address when precise (Precise event)mem_load_l3_miss_retired.remote_pmmRetired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event)Retired instructions with at least 1 uncacheable load or Bus Lock Supports address when precise (Precise event)Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1 Supports address when precise (Precise event)Retired load instructions with L1 cache hits as data sources Supports address when precise (Precise event)Retired load instructions missed L1 cache as data sources Supports address when precise (Precise event)Retired load instructions with L2 cache hits as data sources Supports address when precise (Precise event)Retired load instructions missed L2 cache as data sources Supports address when precise (Precise event)Retired load instructions with L3 cache hits as data sources Supports address when precise (Precise event)Retired load instructions missed L3 cache as data sources Supports address when precise (Precise event)Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches Supports address when precise (Precise event)Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socketocr.demand_code_rd.l3_hit.snoop_hitmCounts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the dataocr.demand_code_rd.snc_cache.hit_with_fwdCounts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_code_rd.snc_cache.hitmCounts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeCounts demand data reads that hit in the L3 or were snooped from another core's caches on the same socketocr.demand_data_rd.l3_hit.snoop_hit_no_fwdCounts demand data reads that resulted in a snoop that hit in another core, which did not forward the dataocr.demand_data_rd.l3_hit.snoop_hit_with_fwdCounts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreocr.demand_data_rd.l3_hit.snoop_hitmCounts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the dataocr.demand_data_rd.remote_cache.snoop_hit_with_fwdCounts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreocr.demand_data_rd.remote_cache.snoop_hitmCounts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the dataocr.demand_data_rd.snc_cache.hit_with_fwdCounts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_data_rd.snc_cache.hitmCounts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socketocr.demand_rfo.l3_hit.snoop_hitmCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the dataocr.demand_rfo.snc_cache.hit_with_fwdCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socketCounts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socketCounts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socketCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socketocr.reads_to_core.l3_hit.snoop_hit_no_fwdCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the dataocr.reads_to_core.l3_hit.snoop_hit_with_fwdCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreocr.reads_to_core.l3_hit.snoop_hitmCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the dataocr.reads_to_core.remote_cache.snoop_fwdCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified)ocr.reads_to_core.remote_cache.snoop_hit_with_fwdCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting coreocr.reads_to_core.remote_cache.snoop_hitmCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the dataocr.reads_to_core.snc_cache.hit_with_fwdCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeocr.reads_to_core.snc_cache.hitmCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) modeCounts streaming stores that hit in the L3 or were snooped from another core's caches on the same socketDemand and prefetch data readsCounts memory transactions sent to the uncoreoffcore_requests.demand_code_rdCounts cacheable and non-cacheable code reads to the coreoffcore_requests.demand_data_rdDemand Data Read requests sent to uncoreDemand RFO requests including regular RFOs, locks, ItoMoffcore_requests_outstanding.all_data_rdFor every cycle, increments by the number of outstanding data read requests pendingoffcore_requests_outstanding.cycles_with_data_rdCycles where at least 1 outstanding data read request is pendingoffcore_requests_outstanding.cycles_with_demand_code_rdCycles with outstanding code read requests pendingoffcore_requests_outstanding.cycles_with_demand_rfoCycles where at least 1 outstanding Demand RFO request is pendingoffcore_requests_outstanding.demand_code_rdFor every cycle, increments by the number of outstanding code read requests pendingoffcore_requests_outstanding.demand_data_rdFor every cycle, increments by the number of outstanding demand data read requests pendingCounts bus locks, accounts for cache line split locks and UC locksCycles the queue waiting for offcore responses is fullNumber of PREFETCHNTA instructions executedNumber of PREFETCHW instructions executedNumber of PREFETCHT0 instructions executedNumber of PREFETCHT1 or PREFETCHT2 instructions executedCounts all microcode FP assistsfp_arith_inst_retired.128b_packed_doubleCounts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementfp_arith_inst_retired.128b_packed_singleNumber of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementfp_arith_inst_retired.256b_packed_doubleCounts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementfp_arith_inst_retired.256b_packed_singleCounts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elementfp_arith_inst_retired.512b_packed_doubleCounts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementfp_arith_inst_retired.512b_packed_singleCounts number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of SSE/AVX computational 256-bit packed single precision and 512-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elementNumber of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per elementfp_arith_inst_retired.scalar_doubleCounts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementfp_arith_inst_retired.scalar_singleCounts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per elementNumber of any Vector retired FP arithmetic instructionsCounts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front endStalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]Decode Stream Buffer (DSB)-to-MITE transitions countdsb2mite_switches.penalty_cyclesDSB-to-MITE switch true penalty cyclesRetired Instructions who experienced DSB miss (Precise event)Retired Instructions who experienced a critical DSB miss (Precise event)Retired Instructions who experienced iTLB true miss (Precise event)Retired Instructions who experienced Instruction L1 Cache true miss (Precise event)Retired Instructions who experienced Instruction L2 Cache true miss (Precise event)Retired instructions after front-end starvation of at least 1 cycle (Precise event)frontend_retired.latency_ge_128Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_16Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall (Precise event)Retired instructions after front-end starvation of at least 2 cycles (Precise event)frontend_retired.latency_ge_256Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_2_bubbles_ge_1Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_32Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall (Precise event)Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_512Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall (Precise event)frontend_retired.latency_ge_64Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall (Precise event)Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall (Precise event)Retired Instructions who experienced STLB (2nd level TLB) true miss (Precise event)Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularityInstruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularityCycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]Cycles Decode Stream Buffer (DSB) is delivering any UopCycles DSB is delivering optimal number of UopsUops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pathCycles MITE is delivering any UopCycles MITE is delivering optimal number of UopsUops delivered to Instruction Decode Queue (IDQ) from MITE pathNumber of switches from DSB or MITE to the MSUops delivered to IDQ while MS is busyUops not delivered by IDQ when backend of the machine is not stalledidq_uops_not_delivered.cycles_0_uops_deliv.coreCycles when no uops are not delivered by the IDQ when backend of the machine is not stalledidq_uops_not_delivered.cycles_fe_was_okCycles when optimal number of uops was delivered to the back-end when the back-end is not stalledExecution stalls while L3 cache miss demand load is outstandingmachine_clears.memory_orderingNumber of machine clears due to memory ordering conflictsmem_trans_retired.load_latency_gt_128Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles Supports address when precise (Must be precise)mem_trans_retired.load_latency_gt_16Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles Supports address when precise (Must be precise)mem_trans_retired.load_latency_gt_256Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles Supports address when precise (Must be precise)mem_trans_retired.load_latency_gt_32Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles Supports address when precise (Must be precise)mem_trans_retired.load_latency_gt_4Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles Supports address when precise (Must be precise)mem_trans_retired.load_latency_gt_512Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles Supports address when precise (Must be precise)mem_trans_retired.load_latency_gt_64Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles Supports address when precise (Must be precise)mem_trans_retired.load_latency_gt_8Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles Supports address when precise (Must be precise)Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 cachesocr.demand_code_rd.l3_miss_localCounts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyCounts demand data reads that were not supplied by the local socket's L1, L2, or L3 cachesocr.demand_data_rd.l3_miss_localCounts demand data reads that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 cachesCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socketCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 cachesocr.hwpf_l1d_and_swpf.l3_miss_localCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyCounts hardware prefetches to the L3 only that missed the local socket's L1, L2, and L3 cachesCounts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyCounts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyCounts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 cachesCounts miscellaneous requests, such as I/O and un-cacheable accesses that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyCounts hardware and software prefetches to all cache levels that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 cachesocr.reads_to_core.l3_miss_localCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by the local socketocr.reads_to_core.l3_miss_local_socketCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC ClusterCounts streaming stores that missed the local socket's L1, L2, and L3 cachesocr.streaming_wr.l3_miss_localCounts streaming stores that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline is homed locallyoffcore_requests.l3_miss_demand_data_rdCounts demand data read requests that miss the L3 cacheoffcore_requests_outstanding.cycles_with_l3_miss_demand_data_rdCycles where at least one demand data read request known to have missed the L3 cache is pendingoffcore_requests_outstanding.l3_miss_demand_data_rd_ge_6Cycles where the core is waiting on at least 6 outstanding demand data read requests known to have missed the L3 cacheNumber of times an RTM execution abortedNumber of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)Number of times an RTM execution aborted due to incompatible memory typertm_retired.aborted_unfriendlyNumber of times an RTM execution aborted due to HLE-unfriendly instructionsNumber of times an RTM execution successfully committedNumber of times an RTM execution startedCounts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional regionNumber of times an instruction execution caused the transactional nest count supported to be exceededSpeculatively counts the number of TSX aborts due to a data capacity limitation for transactional readsSpeculatively counts the number of TSX aborts due to a data capacity limitation for transactional writesNumber of times a transactional abort was signaled due to a data conflict on a transactionally accessed addressCore cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo scheduleCore cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo scheduleCore cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo scheduleHit snoop reply with data, line invalidatedHitM snoop reply with data, line invalidatedHit snoop reply without sending the data, line invalidatedHit snoop reply with data, line kept in Shared stateHitM snoop reply with data, line kept in Shared stateHit snoop reply without sending the data, line kept in Shared stateocr.demand_code_rd.any_responseCounts demand instruction fetches and L1 instruction cache prefetches that have any type of responseCounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAMCounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC ClusterCounts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeocr.demand_data_rd.any_responseCounts demand data reads that have any type of responseCounts demand data reads that were supplied by DRAMCounts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC ClusterCounts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC ClusterCounts demand data reads that were supplied by PMMocr.demand_data_rd.remote_dramCounts demand data reads that were supplied by DRAM attached to another socketCounts demand data reads that were supplied by PMM attached to another socketCounts demand data reads that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeCounts demand data reads that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of responseCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAMCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC ClusterCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC ClusterCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMMCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to another socketCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeCounts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAMocr.hwpf_l1d_and_swpf.local_dramCounts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC ClusterCounts hardware prefetch (which bring data to L2) that have any type of responseCounts hardware prefetches to the L3 only that have any type of responseCounts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socketCounts full cacheline writes (ItoM) that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socketCounts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of responseocr.reads_to_core.any_responseCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of responseCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAMCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC ClusterCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Clusterocr.reads_to_core.local_socket_dramCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Clusterocr.reads_to_core.local_socket_pmmCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC ClusterCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the local socket's L1, L2, or L3 caches and were supplied by a remote socketCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to another socketocr.reads_to_core.remote_memoryCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM or PMM attached to another socketCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to another socketCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeCounts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM on a distant memory controller of this socket when the system is in SNC (sub-NUMA cluster) modeCounts streaming stores that have any type of responseCounts Demand RFOs, ItoM's, PREFECTHW's, Hardware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted in a store to Memory (DRAM or PMM)Cycles when divide unit is busy executing divide or square root operationsNumber of occurrences where a microcode assist is invoked by hardwareAll branch instructions retired (Precise event)Conditional branch instructions retired (Precise event)Not taken branch instructions retired (Precise event)Taken conditional branch instructions retired (Precise event)Far branch instructions retired (Precise event)Indirect near branch instructions retired (excluding returns) (Precise event)Direct and indirect near call instructions retired (Precise event)Return instructions retired (Precise event)Taken branch instructions retired (Precise event)All mispredicted branch instructions retired (Precise event)Mispredicted conditional branch instructions retired (Precise event)Mispredicted non-taken conditional branch instructions retired (Precise event)number of branch instructions retired that were mispredicted and taken (Precise event)All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch) (Precise event)Mispredicted indirect CALL instructions retired (Precise event)Number of near branch instructions retired that were mispredicted and taken (Precise event)This event counts the number of mispredicted ret instructions retired. Non PEBS (Precise event)Cycle counts are evenly distributed between active threads in the Corecpu_clk_unhalted.one_thread_activeCore crystal clock cycles when this thread is unhalted and the other thread is haltedcpu_clk_unhalted.ref_distributedCore crystal clock cycles. Cycle counts are evenly distributed between active threads in the CoreReference cycles when the core is not in halt stateCore crystal clock cycles when the thread is unhaltedCore cycles when the thread is not in halt stateThread cycles when thread is not in halt statecycle_activity.cycles_l1d_missCycles while L1 cache miss demand load is outstandingCycles while L2 cache miss demand load is outstandingCycles while memory subsystem has an outstanding loadcycle_activity.stalls_l1d_missExecution stalls while L1 cache miss demand load is outstandingExecution stalls while L2 cache miss demand load is outstandingExecution stalls while memory subsystem has an outstanding loadCycles total of 1 uop is executed on all ports and Reservation Station was not emptyCycles total of 2 uops are executed on all ports and Reservation Station was not emptyCycles total of 3 uops are executed on all ports and Reservation Station was not emptyCycles total of 4 uops are executed on all ports and Reservation Station was not emptyCycles where the Store Buffer was full and no loads caused an execution stallStalls caused by changing prefix length of the instruction. [This event is alias to DECODE.LCP]Instruction decoders utilized in a cycleNumber of instructions retired. Fixed Counter - architectural event (Precise event)Number of instructions retired. General Counter - architectural event (Precise event)Number of all retired NOP instructions (Precise event)Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution (Precise event)Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stallCounts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered pathCore cycles the allocator was stalled due to recovery from earlier clear event for this threadTMA slots where uops got droppedThe number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in useLoads blocked due to overlapping with a preceding store that cannot be forwardedld_blocks_partial.address_aliasFalse dependencies due to partial compare on addressCounts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetchCycles Uops delivered by the LSD, but didn't come from the decoderCycles optimal number of Uops delivered by the LSD, but did not come from the decoderNumber of Uops delivered by the LSDNumber of machine clears (nukes) of any typeSelf-modifying code (SMC) detectedIncrements whenever there is an update to the LBR arrayNumber of retired PAUSE instructions. This event is not supported on first SKL and KBL productsCycles stalled due to no store buffers available. (not including draining form sync)Counts cycles where the pipeline is stalled due to serializing operationsCycles when Reservation Station (RS) is empty for the threadCounts end of periods where the Reservation Station (RS) was emptyTMA slots where no uops were being issued due to lack of back-end resourcesTMA slots available for an unhalted logical processor. Fixed counter - architectural eventTMA slots available for an unhalted logical processor. General counter - architectural eventNumber of uops decoded out of instructions exclusively fetched by decoder 0Number of uops executed on port 0Number of uops executed on port 1Number of uops executed on port 2 and 3Number of uops executed on port 4 and 9Number of uops executed on port 5Number of uops executed on port 6Number of uops executed on port 7 and 8uops_executed.core_cycles_ge_1Cycles at least 1 micro-op is executed from any thread on physical coreuops_executed.core_cycles_ge_2Cycles at least 2 micro-op is executed from any thread on physical coreuops_executed.core_cycles_ge_3Cycles at least 3 micro-op is executed from any thread on physical coreuops_executed.core_cycles_ge_4Cycles at least 4 micro-op is executed from any thread on physical coreCycles where at least 1 uop was executed per-threadCycles where at least 2 uops were executed per-threadCycles where at least 3 uops were executed per-threadCycles where at least 4 uops were executed per-threadCounts number of cycles no uops were dispatched to be executed on this threadCounts the number of uops to be executed per-thread each cycleCounts the number of x87 uops dispatchedCycles when RAT does not issue Uops to RS for the threaduops_issued.vector_width_mismatchUops inserted at issue-stage in order to preserve upper bits of vector registersCycles without actually retired uopsCycles with less than 10 actually retired uopsLoads that miss the DTLB and hit the STLBCycles when at least one PMH is busy with a page walk for a demand loaddtlb_load_misses.walk_completedLoad miss in all TLB levels causes a page walk that completes. (All page sizes)dtlb_load_misses.walk_completed_1gPage walks completed due to a demand data load to a 1G pagedtlb_load_misses.walk_completed_2m_4mPage walks completed due to a demand data load to a 2M/4M pagedtlb_load_misses.walk_completed_4kPage walks completed due to a demand data load to a 4K pageNumber of page walks outstanding for a demand load in the PMH each cycleStores that miss the DTLB and hit the STLBCycles when at least one PMH is busy with a page walk for a storedtlb_store_misses.walk_completedStore misses in all TLB levels causes a page walk that completes. (All page sizes)dtlb_store_misses.walk_completed_1gPage walks completed due to a demand data store to a 1G pagedtlb_store_misses.walk_completed_2m_4mPage walks completed due to a demand data store to a 2M/4M pagedtlb_store_misses.walk_completed_4kPage walks completed due to a demand data store to a 4K pagedtlb_store_misses.walk_pendingNumber of page walks outstanding for a store in the PMH each cycleInstruction fetch requests that miss the ITLB and hit the STLBCycles when at least one PMH is busy with a page walk for code (instruction fetch) requestCode miss in all TLB levels causes a page walk that completes. (All page sizes)itlb_misses.walk_completed_2m_4mCode miss in all TLB levels causes a page walk that completes. (2M/4M)Code miss in all TLB levels causes a page walk that completes. (4K)Number of page walks outstanding for an outstanding code request in the PMH each cycleDTLB flush attempts of the thread-specific entriesunhalted-reference-cycles~system=1~user=0cpu_clk_unhalted.ref_p~system=1~user=0mem_trans_retired.load_latencyEstimated time stalled on DTLB misses requiring a tablewalk. Does not include time related to STLB hits.fp_arith_inst_retired.scalar_double~umask=0x3Floating-point scalar micro-ops that retiredfp_arith_inst_retired.128b_packed_double~umask=0x3cFloating-point vector micro-ops that retiredl1d_pend_miss.pending_cycles_anyoffcore_requests_outstanding.cycles_with_demand_data_rdoffcore_requests_outstanding.demand_data_rd_ge_6lock_cycles.cache_lock_durationidq_uops_not_delivered.cycles_le_1_uop_deliv.coreidq_uops_not_delivered.cycles_le_2_uop_deliv.coreidq_uops_not_delivered.cycles_le_3_uop_deliv.coreexe_activity.exe_bound_0_portsuops_executed.cycles_ge_1_uop_execuops_executed.cycles_ge_2_uops_execuops_executed.cycles_ge_3_uops_execuops_executed.cycles_ge_4_uops_execuops_executed.core_cycles_nonedtlb_load_misses.walk_durationcpu_clk_thread_unhalted.one_thread_activedtlb_store_misses.walk_durationoffcore_requests_outstanding.demand_code_rd_cyclesoffcore_requests_outstanding.demand_rfo_cycleslock_cycles.split_lock_uc_lock_durationuops_executed_port.port_0_coreuops_executed_port.port_1_coreuops_executed_port.port_2_coreuops_executed_port.port_3_coreuops_executed_port.port_4_coreuops_executed_port.port_5_coreuops_executed_port.port_6_coreuops_executed_port.port_7_corecycle_activity.cycles_l2_pendingcycle_activity.cycles_ldm_pendingcycle_activity.cycles_no_executecycle_activity.cycles_l1d_pendinguops_retired.core_stall_cyclesDTLB Misses x 30: Estimated Stallscycle_activity.cycles_l2_pending_cyclescycle_activity.cycles_ldm_pending_cyclescycle_activity.cycles_l1d_pending_cyclesdtlb_load_misses.demand_ld_walk_completeddtlb_load_misses.demand_ld_walk_durationpartial_rat_stalls.flags_merge_uoppartial_rat_stalls.flags_merge_uop_cyclespartial_rat_stalls.slow_lea_windowresource_stalls2.all_prf_controloffcore_requests_outstanding.demand_data_rd_cyclesoffcore_requests_outstanding.all_data_rd_cyclesidq_uops_not_delivered.cycles_ge_1_uop_deliv.corecycle_activity.stalls_l2_pendingcycle_activity.stalls_ldm_pendingcycle_activity.cycles_no_dispatchcycle_activity.stalls_l1d_pendingl1d_blocks.bank_conflict_cyclesmem_load_retired.llc_unshared_hitL3 Cache Hit w/o Snoop x 35: Est. Stallsmem_load_retired.other_core_l2_hit_hitmL3 Cache Hit w/Snoop x 74: Est. StallsL3 Cache Misses x 180: Estimated StallsPartial Address Aliases x 3: Est. Stallsuops_executed.port234~cmask=1~inv=1uops_retired.any~cmask=1~inv=1memory_disambiguation.watch_cycleshw_int.cycles_pending_and_maskedl1d_pend_miss.load_buffers_fulloffcore_requests_outstanding.demand.read_dataoffcore_requests_outstanding.demand.read_codeoffcore_requests_outstanding.demand.rfooffcore_requests_outstanding.any.readsnoopq_requests_outstanding.datasnoopq_requests_outstanding.invalidatesnoopq_requests_outstanding.coders_uops_dispatched~cmask=1~inv=1rat_stalls.other_serialization_stallsTC_deliver_mode~threshold=0xf~complement=1~compare=1BSQ_cache_reference~emask=0x0507BSQ_cache_reference~emask=0x0007BSQ_cache_reference~emask=0x0500(Backtracking traversed a branch target)(Backtracking failed to find a valid branch target)(Module with trigger PC not compiled with -xhwcprof)mem_trans_retired.precise_storeinsts,,cycles,,+l2m_latency,,dtlbm_stallinsts,,cycles,,l3m_stall,,dtlbm_stallinsts,,cycles,,+l2m_latency,,dtlbminsts,,cycles,,l2m_stall,,dtlbm_stallinsts,,cycles,,dTLB-load-missesuser_time,,system_time,,cycles,,insts,,llmPentium Pro with MMX, Pentium IIIntel Arch PerfMon v3 on Family 6 Model 26Intel Arch PerfMon v3 on Family 6 Model 30Intel Arch PerfMon v3 on Family 6 Model 31Intel Arch PerfMon v3 on Family 6 Model 46Intel Arch PerfMon v3 on Family 6 Model 37Intel Arch PerfMon v3 on Family 6 Model 44Intel Arch PerfMon v3 on Family 6 Model 47Intel Arch PerfMon v3 on Family 6 Model 42Intel Arch PerfMon v3 on Family 6 Model 45Intel Arch PerfMon v3 on Family 6 Model 58Intel Arch PerfMon v3 on Family 6 Model 62Intel Arch PerfMon v3 on Family 6 Model 28Intel Arch PerfMon v3 on Family 6 Model 60Intel Arch PerfMon v3 on Family 6 Model 63Intel Arch PerfMon v3 on Family 6 Model 69Intel Arch PerfMon v3 on Family 6 Model 70Intel Arch PerfMon v3 on Family 6 Model 61Intel Arch PerfMon v3 on Family 6 Model 71Intel Arch PerfMon v3 on Family 6 Model 79Intel Arch PerfMon v3 on Family 6 Model 86Intel Arch PerfMon v4 on Family 6 Model 78Intel Arch PerfMon v4 on Family 6 Model 85Intel Arch PerfMon v4 on Family 6 Model 94dtlb_load_misses.miss_causes_a_walkl2_rqsts.all_demand_referencescpu_clk_thread_unhalted.ref_xclkcpu_clk_thread_unhalted.ref_xclk_anydtlb_store_misses.miss_causes_a_walktx_mem.abort_hle_store_to_elided_locktx_mem.abort_hle_elision_buffer_not_emptytx_mem.abort_hle_elision_buffer_mismatchtx_mem.abort_hle_elision_buffer_unsupported_alignmenttx_mem.hle_elision_buffer_fulloffcore_requests_outstanding.demand_rfooffcore_requests_outstanding.l3_miss_demand_data_rditlb_misses.miss_causes_a_walkoffcore_requests_buffer.sq_fullhle_retired.aborted_unfriendlymem_load_l3_hit_retired.xsnp_hitmem_load_l3_hit_retired.xsnp_hitmdtlb_load_misses.pde_cache_missint_misc.recovery_cycles_occurrencesdtlb_store_misses.pde_cache_missmove_elimination.int_eliminatedmove_elimination.simd_eliminatedmove_elimination.int_not_eliminatedmove_elimination.simd_not_eliminatedoffcore_requests_outstanding.demand_data_rd_ge_6 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